Revision History - 5.3 English - PG243

Video Mixer LogiCORE IP Product Guide (PG243)
Document ID
PG243
Release Date
2025-05-29
Version
5.3 English

The following table shows the revision history for this document.

Section Revision Summary
05/29/2025 Version 5.3
Y_U_V8 Added the section.
Y_U_V10 Added the section.
Y_U_V12 Added the section.
Layer Buffer Plane 1 (0x0#40), Layer Plane 2 Buffer (0x0#4C), and Layer Plane 3 Buffer (0x0#58) Registers Updated the section.
User Parameters Updated the table.
01/02/2024 Version 5.2
IP Facts Updated the section
N/A Editorial changes
10/19/2022 Version 5.2
Layer Width (0x0#18) Register Updated the section
Design Flow Steps Added note for Line Buffer Width
04/27/2022 Version 5.2
Top-Level Registers Updated the section
CSC Coefficient Registers Updated the section
Control (0x0000) Register Updated the section
10/27/2021 Version 5.2
N/A Updated to support eight samples per clock.
08/06/2021 Version 5.2
Table 1 Updated
Upgrading Updated
02/04/2021 Version 5.1
Example Design Updated with Vitis application flow for v5.1
06/10/2020 Version 5.0
N/A
  • Added CSC Coefficient Registers table.
  • Added Enable CSC Coefficient Registers parameter in the GUI.
  • Updated Figure 4-1.
  • Updated Table 4-1.
  • Updated Upgrading in the Vivado Design Suite section.
12/06/2019 Version 4.0
N/A
  • Updated for Example Design with Vitis application flow.
  • Added Layer 0 registers.
05/22/2019 Version 4.0
N/A Updated to support up to 16 overlay layers.
12/05/2018 Version 3.0
N/A Updated to show one main layer and eight overlay layers support.
04/04/2018 Version 3.0
N/A
  • Updated to support 8 overlay layers.
  • Added support for BGR8.
10/04/2017 Version 2.0
N/A
  • Added second buffer pointer for semi-planar formats.
  • Added 64-bit address support for memory mapped AXI4 interface.
  • Register map offsets re-ordered to handle both 32 and 64-bit addressing.
  • Added UYVY8 and BGRX8 memory formats.
  • Added per pixel alpha streaming formats RGBA and YUVA444.
04/05/2017 Version 1.0
N/A Added BGRA8, Y_UV10, Y_UV10_420, Y8, and Y10 to Memory Mapped AXI4 Interface.
10/05/2016 Version 1.0
N/A
  • Added YUV 4:2:0.
  • Updated Features in IP Facts.
  • Updated SDK directory link in IP Facts table.
  • Updated Feature Summary section.
  • Added RGBA8 to Y_UV8_420 sections.
  • Updated description for Layer Buffer (0x0048+i*8) Register section.
  • Added 0x4 0000 Logo Alpha Buffer table.
  • Updated description in Logo Red Buffer (0x1 0000) Register.
  • Updated description in General Design Guidelines section.
  • Updated Alpha Blending section.
  • Updated description to Layer Settings and Logo Layer Settings in Design Flow Steps chapter.
  • Added Enable Logo per Pixel Alpha in Vivado IDE Parameter to User Parameter Relationship table.
  • Updated Prerequisites section.
04/06/2016 Version 1.0
N/A Initial release.