Revision History - 5.2 English

MIPI CSI-2 Receiver Subsystem Product Guide (PG232)

Document ID
PG232
Release Date
2022-10-19
Version
5.2 English

The following table shows the revision history for this document.

Date

Version

Revision

10/19/2022

5.2

Added new register to allow Dynamic VC selection.

04/26/2022

5.1

Active_lanes port added when CSI-2 Controller Register Interface Disabled

ZCU102 Application Example Design Overview enhanced to support 4K60 on HDMI output.

11/17/2021

5.1

Updated examples in Clocking section.

Updated Pixel Format and Include Video Format Bridge (VFB) options in Configuration Tab .

Updated This Figure .

07/14/2021

5.1

Added Tclk-Post Requirement in Overview .

Added a new note for line rates that are >1500 in Designing with the Subsystem .

Added a new parameter in Configuration Tab .

Updated Table: Vivado IDE Parameter to User Parameter Relationship .

Updated the Running the Design on Hardware section.

Updated Implementing the Example Design section.

Updated Hardware Validation section.

01/08/2021

5.1

General updates and corrections for Versal ACAP support.

Revised examples in Clocking section.

Added YUV420-8bit support.

07/16/2020

5.0

Added support for Versal ACAP.

06/12/2020

5.0

Updated the register space information to include VCX Frame Error bit in the IER

Updated the Interoperability testing for UltraScale+ devices.

Example Design for Vitis updated.

11/22/2019

4.1

Updated the register space information to include ISR and IER bits for skewcalhs.

Added Application example design for SP701 board.

Added CSI2 Controller Register Interface GUI option to aid resource optimization.

Removed AXI IIC Option.

07/02/2019

4.0

Extended line rate support up to 2500 Mb/s.

Added support for Deskew sequence detection at MIPI D-PHY for UltraScale+ devices.

Corrected the doc version.

05/22/2019

4.1

Updated the minimum video clock requirement in chapter 3.

Added MIPI CSI2 RX Subsystem Latency Calculation.

Corrected Data corruption for certain word counts during RAW20 data type reception.

12/05/2018

4.0

Updated video_out_tdest and emb_nonimg_tdest port size.

Updated Table 2-5 to include VCX Frame Error register, Image Information 1, and Image Information 2 Registers for VC4 to VC15.

Updated Table 1-1 to include RAW16, RAW20, and YUV 422 10 bit data types.

Updated Table 4-1 User Parameters.

Included new GUI options for MIPI CSI-2 Standard v2.0 compatibility in the Configuration Tab.

Updated examples in the Pixel Packing for Multiple Data Types section to match the alignment described in AXI4-Stream Video IP and System Design Guide (UG934).

04/04/2018

3.0

ECC and CRC of long packets are made available on TUSER ports of output stream interfaces.

Added support for additional 7 series devices.

Added dynamic configuration capability for IDELAY Tap values in fixed calibration mode of 7 series.

10/04/2017

3.0

Added Application Example Design to demonstrate a full end-to-end system from capture to display on ZCU102

Added Board automation support for LI-IMX274MIPI-FMC V1.0 FMC model

04/05/2017

2.2

Word Count (WC) corruption limited to current packet. Additional bit in ISR added to report this conditions

MIPI DPHY v3.1 changes integrated

11/30/2016

2.1

Added calibration mode parameters for FIXED and AUTO modes

10/05/2016

2.1

MIPI D-PHY 3.0 changes integrated

Added 7 series support

04/06/2016

2.0

MIPI D-PHY 2.0 changes integrated

Shared logic support

Video Format Bridge core changes to support RAW8 and User Defined Byte-based Data at all times along with the Vivado IDE selected data type.

11/18/2015

1.0

Initial Xilinx release.