MIPI CSI-2 RX Controller Core Registers - 5.2 English

MIPI CSI-2 Receiver Subsystem Product Guide (PG232)

Document ID
PG232
Release Date
2022-10-19
Version
5.2 English

Table: MIPI CSI-2 RX Controller Core Registers specifies the name, address, and description of each firmware addressable register within the MIPI CSI-2 RX controller core.

Table 2-7: MIPI CSI-2 RX Controller Core Registers

Address Offset

Register Name

Description

0x00

Core Configuration Register

Core configuration options

0x04

Protocol Configuration Register

Protocol configuration options

0x08

Reserved (1)

0x0C

Reserved

0x10

Core Status Register

Internal status of the core

0x14

Reserved

0x18

Reserved

0x1C

Reserved

0x20

Global Interrupt Enable Register

Global interrupt enable registers

0x24

Interrupt Status Register

Interrupt status register

0x28

Interrupt Enable Register

Interrupt enable register

0x2C

Dynamic VC Selection Register

VC selection register

0x30

Generic Short Packet Register

Short packet data

0x34

VCX Frame Error Register

VCX Frame Error Register

0x38

Reserved

0x3C

Clock Lane Information Register

Clock lane status information

Lane<n> Information Registers

0x40

Lane0 Information

Lane 0 status information

0x44

Lane1 Information

Lane 1 status information

0x48

Lane2 Information

Lane 2 status information

0x4C

Lane3 Information

Lane 3 status information

0x50

Reserved

0x54

Reserved

0x58

Reserved

0x5C

Reserved

Image Information 1 Registers (VC0 to VC15) and Image Information 2 Registers (VC0 to VC15)

0x60

Image Information 1 for VC0

Image information 1 of the current processing packet with VC of 0

0x64

Image Information 2 for VC0

Image information 2 of the current processing packet with VC of 0

0x68

Image Information 1 for VC1

Image information 1 of the current processing packet with VC of 1

0x6C

Image Information 2 for VC1

Image information 2 of the current processing packet with VC of 1

0x70

Image Information 1 for VC2

Image information 1 of the current processing packet with VC of 2

0x74

Image Information 2 for VC2

Image information 2 of the current processing packet with VC of 2

0x78

Image Information 1 for VC3

Image information 1 of the current processing packet with VC of 3

0x7C

Image Information 2 for VC3

Image information 2 of the current processing packet with VC of 3

0x80

Image Information 1 for VC4

Image information 1 of the current processing packet with VC of 4

0x84

Image Information 2 for VC4

Image information 2 of the current processing packet with VC of 4

0x88

Image Information 1 for VC5

Image information 1 of the current processing packet with VC of 5

0x8C

Image Information 2 for VC5

Image information 2 of the current processing packet with VC of 5

0x90

Image Information 1 for VC6

Image information 1 of the current processing packet with VC of 6

0x94

Image Information 2 for VC6

Image information 2 of the current processing packet with VC of 6

0x98

Image Information 1 for VC7

Image information 1 of the current processing packet with VC of 7

0x9C

Image Information 2 for VC7

Image information 2 of the current processing packet with VC of 7

0xA0

Image Information 1 for VC8

Image information 1 of the current processing packet with VC of 8

0xA4

Image Information 2 for VC8

Image information 2 of the current processing packet with VC of 8

0xA8

Image Information 1 for VC9

Image information 1 of the current processing packet with VC of 9

0xAC

Image Information 2 for VC9

Image information 2 of the current processing packet with VC of 9

0xB0

Image Information 1 for VC10

Image information 1 of the current processing packet with VC of 10

0xB4

Image Information 2 for VC10

Image information 2 of the current processing packet with VC of 10

0xB8

Image Information 1 for VC11

Image information 1 of the current processing packet with VC of 11

0xBC

Image Information 2 for VC11

Image information 2 of the current processing packet with VC of 11

0xC0

Image Information 1 for VC12

Image information 1 of the current processing packet with VC of 12

0xC4

Image Information 2 for VC12

Image information 2 of the current processing packet with VC of 12

0xC8

Image Information 1 for VC13

Image information 1 of the current processing packet with VC of 13

0xCC

Image Information 2 for VC13

Image information 2 of the current processing packet with VC of 13

0xD0

Image Information 1 for VC14

Image information 1 of the current processing packet with VC of 14

0xD4

Image Information 2 for VC14

Image information 2 of the current processing packet with VC of 14

0xD8

Image Information 1 for VC15

Image information 1 of the current processing packet with VC of 15

0xDC

Image Information 2 for VC15

Image information 2 of the current processing packet with VC of 15

Notes:

1. Access type and reset value for all the reserved bits in the registers is read-only with value 0.

2. Register accesses should be word aligned and there is no support for a write strobe. WSTRB is not used internally.

3. Only the lower 7-bits (6:0) of the read and write address of the AXI4-Lite interface are decoded. This means that accessing address 0x00 and 0x80 results in reading the same address of 0x00.

4. Reads and writes to addresses outside this table do not return an error.