Implementing the Example Design

Note: The figures in this chapter are illustrations of the Vivado Integrated Design Environment (IDE). The layout depicted here might vary from the current version.

1. Open the Vivado Design Suite.

The Vivado IDE Getting Started page contains links to open or create projects and to view documentation.

Figure 5-13: Vivado IDE - Getting Started
X-Ref Target - Figure 5-13

2. In the Getting Started page, click Create Project to start the New Project wizard.

3. In the Project Name page, name the new project and enter the project location. Make sure to check the Create project subdirectory option and click Next .

4. In the Project Type page, specify the type of project to create as RTL Project, make sure to Uncheck the Do not specify sources at this time option, and click Next .

5. In the Add Sources page, click Next .

6. In the Add Existing IP (optional) dialog box, click Next .

7. In the Add Constraints (optional) dialog box, click Next .

Figure 5-14: Vivado IDE - Create New Project
X-Ref Target - Figure 5-14

In the Default Part dialog box, click Boards to specify the board for the target device (ZCU102, SP701, and VCK190 boards are supported). Then click Next .

Figure 5-15: Vivado IDE - Default Part
X-Ref Target - Figure 5-15

9. Review the New Project Summary page. Verify that the data appears as expected, per the steps above, and click Finish .

Figure 5-16: Vivado IDE - New Project Summary
X-Ref Target - Figure 5-16

10. Click IP Catalog and select MIPI CSI-2 RX Subsystem under Video Connectivity, then double click on it.

Figure 5-17: Vivado IDE - IP Catalog
X-Ref Target - Figure 5-17

° For the Application Example Design flow, IP configuration is based on options selected in the Application Example Design tab.

11. You can rename the IP component name.Configure the MIPI CSI-2 RX Subsystem Application Example Design tab to select the ZCU102, SP701, or VCK190 board-based design, then click OK .

Figure 5-18: Vivado IDE - Customize IP
X-Ref Target - Figure 5-18

The Generate Output Products dialog box appears.

12. Click Generate . You can optionally click Skip if you want to skip generating the output products.

Figure 5-19: Vivado IDE - Generate Output Products
X-Ref Target - Figure 5-19

13. Right click on the MIPI CSI-2 Rx Subsystem component under Design source, and click Open IP Example Design .

Note: Because this step involves the generation of the complete system including multiple subsystems, it will take some time to completely build the design.

Figure 5-20: Vivado IDE - Open IP Example Design
X-Ref Target - Figure 5-20

14. Choose the target project location, then click OK .

15.

Figure 5-21: Open IP Example Design - Select Example Project Directory
X-Ref Target - Figure 5-21

The overall system IP integrator block diagram of the ZCU102, SP701, or VCK190 board-based application example design is generated depending on the GUI option selected. You can choose to Run Synthesis, Implementation, or Generate Bitstream (Generate Device Image for the VCK190 board).

Figure 5-22: Overall System IP Integrator Block Diagram for ZCU12-based Example Design
X-Ref Target - Figure 5-22

Figure 5-23: Overall System IP Integrator Block Diagram for SP701-based Example Design
X-Ref Target - Figure 5-23

Figure 5-24: Overall VCK190 System IP Integrator Block Diagram
X-Ref Target - Figure 5-24

16. Select File > Export > Export hardware (.xsa)

Figure 5-25: Exporting Hardware
X-Ref Target - Figure 5-25

17. Select Tools > Launch Vitis IDE . Browse to your project location.

18. To create a new platform project using the generated .xsa file, click on the Create new platform tab in the Vitis window and follow the steps shown in This Figure to This Figure .

Figure 5-26: Create a New Platform
X-Ref Target - Figure 5-26

Implementing the Example Design - 5.2 English

MIPI CSI-2 Receiver Subsystem Product Guide (PG232)