Image Information 1 Registers (VC0 to VC15) - 5.2 English

MIPI CSI-2 Receiver Subsystem Product Guide (PG232)

Document ID
PG232
Release Date
2022-10-19
Version
5.2 English

The Image Information 1 registers are described in Table: Image Information 1 Registers (0x60, 0x68, 0x70, 0x78) and provide image information for line count and byte count per VC. The byte count gets updated whenever a long packet (from Data Types 0x18 and above) for the corresponding virtual channel is processed by the control FSM. The line count is updated whenever the packet is written into the line buffer.

Table 2-31: Image Information 1 Registers (0x60, 0x68, 0x70, 0x78)

Bits

Name

Reset Value

Access

Description

31–16

Line count

0x0

R

Number of long packets written to line buffer

15–0

Byte count

0x0

R

Byte count of current packet being processed by the control FSM