• Support for 1 to 4 D-PHY lanes
• Line rates ranging from 80 to 3200 Mb/s
• Multiple Data Type support (RAW, RGB, YUV)
• Filtering based on Virtual Channel Identifier
• Support for 1, 2, or 4 pixels per clock at the output as defined in the Xilinx AXI4-Stream Video IP and System Design Guide (UG934) [Ref 2] format
• AXI4-Lite interface for register access to configure different subsystem options
• Dynamic selection of active lanes within the configured lanes during subsystem generation.
• Interrupt generation to indicate subsystem status information
• Internal D-PHY allows direct connection to image sources
• Support for MIPI CSI-2 standard v2.0 features such as VCX, RAW16, and RAW20
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IP Facts Table |
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|---|---|
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Subsystem Specifics |
|
|
Supported Device Family (1) |
UltraScale+™
Versal
®
ACAP
Zynq ® UltraScale+ RFSoC
Zynq
®
-7000 SoC
|
|
Supported User Interfaces |
AXI4-Lite, AXI4-Stream |
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Resources |
|
|
Provided with Subsystem |
|
|
Design Files |
Encrypted RTL |
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Example Design |
Vivado IP Integrator |
|
Test Bench |
Not Provided |
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Constraints File |
XDC |
|
Simulation Model |
Not Provided |
|
Supported
|
Standalone and Linux |
|
Tested Design Flows (3) |
|
|
Design Entry |
Vivado® Design Suite |
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Simulation |
For supported simulators, see the
|
|
Synthesis |
Vivado Synthesis |
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Support |
|
|
Release Notes and Known Issues |
Master Answer Record: 65242 |
|
All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775 |
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Notes: 1. For a complete list of supported devices, see the Vivado IP catalog. 2. Standalone driver details can be found in the Vitis directory (Vitis IDE>Help>Xilinx OS and Libraries Help>BSP and Libraries Document Collection (UG643)). Linux OS and driver support information is available from the Xilinx Wiki page .
3.
For the supported versions of the tools, see the
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