Gen3x16 capability requires a minimum of a -2 speed grade.
| Capability Link Speed | Capability Link Width | Supported Speed Grades |
|---|---|---|
| AMD UltraScale+™ Devices with PCIE4 Block | ||
| Gen1/Gen2 | x1, x2, x4, x8, x16 | -1, -1L, -1LV, -2, -2L, -2LV, -3 |
| Gen3 | x1, x2, x4 | -1, -1L, -1LV, -2, -2L, -2LV, -3 |
| x8 | -1, -2, -2L, -3 | |
| x16 | -2, -2L, -3 | |
| AMD UltraScale+™ Devices with PCIE4C and PCIE4CE Block | ||
| Gen1/Gen2 | x1, x2, x4, x8, x16 | -1, -2, -2L, -2LV, -3 |
| Gen3 | x1, x2, x4 | -1, -2, -2L, -2LV, -3 |
| x8 | -1, -2, -2L, -3 | |
| x16 | -2, -2L, -3 | |
| Gen4 | x1, x2, x4, x8 | -2, -2L, -3 |
Note: Subject to the documented product
features and minimum device requirements, this IP supports AMD UltraScale+™
devices with one or more
PCIE4/PCIE4C/PCIE4CE integrated blocks for PCIe. Based on the available programmable
logic resources, the following are NOT supported even if this IP is supported by the
device architecture:
- Zynq UltraScale+ MPSoC devices ZU5 and smaller
- Kintex UltraScale+ FPGA devices KU3 and smaller
- Artix UltraScale+ FPGA devices AU25P and smaller
Contact Support for information about implementing this IP in devices containing at least one integrated block for PCIe, but are not supported based on the available programmable logic resources.