AXI4-Lite Slave CSR Register Space - 5.0 English

AXI4-Lite Slave CSR Register Space - 5.0 English - PG302

QDMA Subsystem for PCI Express Product Guide (PG302)

Document ID

PG302

Release Date

2024-12-18

Version

5.0 English

The Bridge register space and DMA register space are accessible through the AXI4-Lite Slave CSR interface. This interface is accessible only when csr_prog_done port is set to 1. You must wait until csr_prog_done port it set.

Table 1. AXI4-Lite Slave CSR Register Space
Register Space	AXI4-Lite Slave CSR Interface	Details
Bridge registers	AXI4-Lite Slave CSR Address bit [15] is set to 0	Found in qdma_v5_0_bridge_registers.csv available in the Register Reference File.
DMA registers	AXI4-Lite Slave CSR Address bit [15] is set to 1	Described in QDMA PF Address Register Space and QDMA VF Address Register Space. Note: Through this interface, only the DMA CSR register can be accessed. The DMA Queue space register can only be accessed through AXI4-Lite Slave.