The following table shows the AXI4-Stream transmit interface signals.
| Signal | I/O | Description | Clock Domain |
|---|---|---|---|
| tx_axis_tdata[63 or 31:0] | I | AXI4-Stream data. 32-bit and 64-bit interfaces are available. Bus width depends on the selection of 64-bit or 32-bit interfaces. | tx_clk_out |
| tx_axis_tkeep[7:0 or 3:0] | I | AXI4-Stream Data Control. Bus width depends on selection of 64-bit or 32-bit interfaces. | tx_clk_out |
| tx_axis_tvalid | I | AXI4-Stream Data Valid input | tx_clk_out |
| tx_axis_tuser | I |
AXI4-Stream User Sideband interface.
|
tx_clk_out |
| tx_axis_tlast | I | AXI4-Stream signal indicating End of Ethernet Packet. | tx_clk_out |
| tx_parityin[7:0] | I | AXI4-Stream user-generated parity. Follows the same data lane mapping as tx_axis_tkeep. | tx_clk_out |
| tx_axis_tready | O | AXI4-Stream acknowledge signal to indicate to start the Data transfer. | tx_clk_out |