Statistics Counters - Statistics Counters - 4.1 English - PG210

The statistics counters provide histograms of the classification of traffic and error counts. These counters can be read either by a 1 on pm_tick or by writing a 1 to the TICK_REG register, depending on the value of MODE_REG[30] (tick_reg_mode_sel). The pm_tick signal is used when MODE_REG[30] = 0 and TICK_REG is used when MODE_REG[30] = 1 (1 = default).

The counters employ an internal accumulator. A write to the TICK_REG register causes the accumulated counts to be pushed to the readable STAT_*_MSB/LSB registers and simultaneously clear the accumulators. Next, the STAT_*_MSB/LSB registers can be read. In this way, all values stored in the statistics counters represent a snapshot over the same time interval.

The STAT_CYCLE_COUNT_MSB/LSB register contains a count of the number of RX core clock cycles between TICK_REG writes. This allows for easy time-interval based statistics.

Statistic counter registers are cleared according to the following conditions:

• Applying s_axi_aresetn clears both TX and RX statistics counter registers
• Applying pm_tick clears both TX and RX statistics counter registers
• Applying rx_reset clears the RX statistics counter registers only
• Applying tx_reset clears the TX statistics counter registers only

These statistics counters will be available for MAC+PCS/PMA-64-bit variants without enabling TX/RX flow control GUI option. For MAC+PCS/PMA 32-bit, Ethernet MAC-64-bit and Preemption variants counters will update only when the TX/RX flow control is enabled in the GUI.