| Signal | I/O | Description | Clock Domain |
|---|---|---|---|
| rx_axis_tdata[63 or 31:0] | O | AXI4-Stream Data to upper layer. Bus width depends on 64-bit or 32-bit selection. | rx_core_clk |
| rx_axis_tkeep[7 or 3:0] | O | AXI4-Stream Data Control to upper layer. Bus width depends on 64-bit or 32-bit selection. | rx_core_clk |
| rx_axis_tvalid | O | AXI4-Stream Data Valid | rx_core_clk |
| rx_axis_tuser | O |
AXI4-Stream User Sideband interface. 1 indicates a bad packet has been received. 0 indicates a good packet has been received. |
rx_core_clk |
| rx_axis_tlast | O | AXI4-Stream signal indicating an end of packet. | rx_core_clk |
| rx_parityout[7:0] | O | AXI4-Stream core-generated parity. Follows the same data lane mapping as rx_axis_tkeep. | rx_core_clk |