The following figures show the block diagrams of the 10G/25G High Speed Ethernet Subsystem, respectively.
Note: GT transceivers are not shown.
Figure 1. 10 Gb/s Core Block Diagram
Figure 2. 25 Gb/s Core Block Diagram
A PCS-only variant of the core is also available. The block diagram is shown in the following figure.
Figure 3. Block Diagram of PCS-Only Core Variant
Additionally, you can optionally generate a 64-bit standalone version of the MAC for 10 Gb/s operation. The block diagram is shown in the following figure.
Figure 4. 64-bit Standalone Version of the MAC for 10 Gb/s
Operation
