Port Descriptions - Port Descriptions - 4.1 English - PG210

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)
Document_ID
PG210
Release_Date
2025-01-31
Version
4.1 English

The following table details the additional signals present when the packet timestamping feature is included.

Table 1. 1588v2 Port List and Descriptions
Name I/O Description Clock Domain
IEEE 1588 Interface – TX Path
ctl_tx_systemtimerin[80-1:0] I System timer input for the TX. In normal clock mode, the 32 LSBs carry nsec and the 48 MSBs carry seconds. In transparent clock mode, bit 63 is expected to be zero, bits 62:16 carry nanoseconds, and bits 15:0 carry fractional nanoseconds. Refer to IEEE 1588v2 for the representational definitions.

This input must be in the TX SerDes clock domain.

 tx_serdes_clk
tx_ptp_tstamp_valid_out O This bit indicates that a valid timestamp is being presented on the TX system interface. tx_clk_out
tx_ptp_tstamp_tag_out[15:0] O Tag output corresponding to tx_ptp_tag_field_in[15:0] tx_clk_out
tx_ptp_tstamp_out[80-1:0] O Timestamp for the transmitted packet SOP corresponding to the time at which it passed the capture plane. Used for 2-step 1588 operation. Time format is the same as timer input. tx_clk_out
tx_ptp_1588op_in[1:0] I

The signal should be valid on the first cycle of the packet. For PCS cores, the first cycle corresponds with the first data word of the packet.

  • 2'b00 – No operation: no timestamp will be taken and the frame will not be modified.
  • 2’b01 – 1-step: a timestamp should be taken and inserted into the frame.
  • 2’b10 – 2-step: a timestamp should be taken and returned to the client using the additional ports of 2-step operation. The frame itself will not be modified.
  • 2’b11 – Reserved: act as No operation.
 tx_clk_out
ctl_tx_ptp_1step_enable I When set to 1, this bit enables 1-step operation. tx_clk_out
tx_ptp_upd_chksum_in   See IEEE 1588 TX/RX Interface Control/Status/Statistics Signals. tx_clk_out
tx_ptp_chksum_offset_in   See IEEE 1588 TX/RX Interface Control/Status/Statistics Signals. tx_clk_out
tx_ptp_tstamp_offset_in_*   See IEEE 1588 TX/RX Interface Control/Status/Statistics Signals. tx_clk_out
ctl_ptp_transpclk_mode I

When set to 1, this input places the timestamping logic into transparent clock mode. In this mode, the system timer input is interpreted as a correction value. The TX will add the correction value to the TX timestamp according to the process defined in IEEE 1588v2. The sign bit of the correction value is assumed to be 0 (positive time).

It is expected that the corresponding incoming PTP packet correction field has already been adjusted with the proper RX timestamp.

 tx_clk_out
tx_ptp_tag_field_in[15:0] I

The usage of this field is dependent on the 1588 operation. The signal should be valid on the first cycle of the packet.

  • For No operation, this field will be ignored.
  • For 1-step and 2-step this field is a tag field. This tag value will be returned to the client with the timestamp for the current frame using the additional ports of 2-step operation. This tag value can be used by software to ensure that the timestamp can be matched with the PTP frame that it sent for transmission.
 tx_clk_out
ctl_tx_latency_* I This is the static latency of the TX path of the core including the GT. The MSB 16 bits indicate the delay in ns and the LSB 16 bits indicate sub ns values. The latency is in binary Q16.16 format.
Note: This is applicable only for the MAC+PCS/PMA 32-bit version and for PCS/PMA 32-bit version.
 tx_clk_out
ctl_tx_lat_adj_enb_* I When this signal is enabled, the delay computation on the TX path takes into account the value provided by the ctl_tx_latency_0 register.
Note: This is applicable only for the MAC+PCS/PMA 32-bit version and for PCS/PMA 32-bit version.
 tx_clk_out
ctl_tx_ptp_latency_adjust[10:0] I This bus can be used to adjust the 1-step TX timestamp with respect to the 2-step timestamp. The units of bits [10:3] are nanoseconds and bits [2:0] are fractional nanoseconds. tx_clk_out
stat_tx_ptp_fifo_write_error O Transmit PTP FIFO write error. A value of 1 on this status indicates that an error occurred during the PTP Tag write. A TX Path reset is required to clear the error. tx_clk_out
stat_tx_ptp_fifo_read_error O Transmit PTP FIFO read error. A value of 1 on this status indicates that an error occurred during the PTP Tag read. A TX Path reset is required to clear the error. tx_clk_out

ctl_tx_timestamp_adj_enb_*

(default value: 1)

 I When this signal is enabled, the delay computation on the TX path takes into account the value obtained from GT DRP read for latency of the TX gearbox FIFO.
Note: This is applicable only for the MAC+PCS/PMA 32-bit version and for PCS/PMA 32-bit version.
 tx_clk_out
tx_period_ns_* O See IEEE 1588 TX/RX Interface Control/Status/Statistics Signals. tx_clk_out
IEEE 1588 Interface – RX Path
ctl_rx_systemtimerin[80-1:0] I System timer input for the RX. Same time format as the TX. This input must be in the same clock domain as the RX SerDes. rx_serdes_clk
rx_ptp_tstamp_out[80-1:0] O Timestamp for the received packet SOP corresponding to the time at which it passed the capture plane. This signal will be valid on the first cycle of the packet. Used for 2-step 1588 operation. rx_core_clk
rx_ptp_tstamp_valid_out_* O This bit indicates that a valid timestamp is being presented on the RX system interface. rx_core_clk
ctl_rx_latency_* I This is the static latency of the RX path of the core including the GT. The MSB 16-bit indicate the delay in ns and the LSB 16-bit indicate sub ns values. The latency is in binary Q16.16 format.
Note: This is applicable only for the MAC+PCS/PMA 32-bit version and for PCS/PMA 32-bit version.
 rx_clk_out

ctl_rx_lat_adj_enb_*

(default value: 1)

 I When this signal is enabled, the delay computation on the RX path takes into account the value provided by the ctl_rx_latency_0 register.
Note: This is applicable only for MAC+PCS/PMA 32-bit version and for PCS/PMA 32-bit version.
 rx_clk_out

ctl_rx_timestamp_adj_enb_*

(default value: 1)

 I When this signal is enabled, the delay computation on the RX path takes into account the value obtained from the GT DRP read for latency of the RX gearbox FIFO.
Note: This is applicable only for the MAC+PCS/PMA 32-bit version and for PCS/PMA 32-bit version.
 rx_clk_out
rx_period_ns_* O See IEEE 1588 TX/RX Interface Control/Status/Statistics Signals. rx_clk_out