- Designed to the Ethernet requirements for 10/25 Gb/s operation specified
by IEEE 802.3 Clause 49, IEEE 802.3by, and the 25G Ethernet Consortium.
- Includes complete Ethernet MAC and PCS/PMA functions or standalone
PCS/PMA for 25 Gb/s operation.
- Includes complete Ethernet MAC and PCS/PMA functions, standalone MAC or
standalone PCS/PMA for 10 Gb/s operation. Includes standalone 64-bit Ethernet MAC.
- Simple packet-oriented user interface.
- Comprehensive statistics gathering.
- Status signals for all major functional indicators.
- Delivered with a top-level wrapper including functional transceiver
wrapper, IP netlist, sample test scripts, and AMD Vivado™ Design Suite tools compile scripts.
- BASE-R PCS sublayer operating at 10.3125 Gb/s or 25.78125 Gb/s.
- Optional clause 74 BASE-KR FEC sublayer.
- Optional Auto-Negotiation/Link Training.
- Optional clause 108 25G Reed-Solomon.
- Forward Error Correction (RS-FEC) sublayer (Soft RS-FEC TX, Hard RS-FEC
RX option to reduce logic utilization by leveraging the embedded 100G RS-FEC function that
exists within the CMAC block in AMD UltraScale+™
devices).
- Custom Preamble mode.
- Optional IEEE 1588 1-step and 2-step timestamping.
- Runtime switchable between 10G and 25G.
- Optional fee-based Time Sensitive Networking (TSN) feature designed to
IEEE standard 802.1 CM:
- Supports interspersing express traffic with low-priority traffic
- Supports frame preemption