Introduction - Introduction - 4.0 English

The DPUCZDX8G IP provides some user-configurable parameters to optimize resource usage and customize different features. Different configurations can be selected for DSP slices, LUT, block RAM, and UltraRAM usage based on the amount of available programmable logic resources. There are also options for additional functions, such as channel augmentation, average pooling, depthwise convolution, and softmax. Furthermore, there is an option to determine the number of DPUCZDX8G cores that will be instantiated in a single DPUCZDX8G IP.

The deep neural network features and the associated parameters supported by the DPUCZDX8G are shown in the following table.

A configuration file named arch.json is generated during the Vivado or Vitis flow. The arch.json file is used by the Vitis AI Compiler for model compilation. If the content of arch.json is changed. Please re-compile the model. For more information of Vitis AI Compiler, see refer to the Vitis AI User Guide (UG1414).

In the Vivado flow, the arch.json file is located at $TRD_HOME/prj/Vivado/srcs/top/ip/top_dpu_0/arch.json.

In the Vitis flow, the arch.json file is located at $TRD_HOME/prj/Vitis/binary_container_1/link/vivado/vpl/prj/prj.gen/sources_1/bd/zcu102_base/ip/zcu102_base_DPUCZDX8G_1_0/arch.json.

Note: $TRD_home = Vitis-AI/dsa/DPU-TRD/

Table 1. DPUCZDX8G Operation and Parameter Support
Features	Description
Convolution	Kernel Sizes	w, h: [1, 16]
	Strides	w, h: [1, 8]
	Padding	w: [0, kernel_w-1] h: [0, kernel_h-1]
	Input Size	Arbitrary
	Input Channel	1~256 * channel_parallel
	Output Channel	1~256 * channel_parallel
	Activation	ReLU, ReLU6, LeakyReLU, Hard Sigmoid and Hard Swish
	Dilation	dilation * input_channel ≤ 256 * channel_parallel && stride_w == 1 && stride_h == 1
	Constraint*	kernel_w * kernel_h * (ceil(input_channel / channel_parallel)) <= bank_depth
Depthwise Convolution	Kernel Sizes	w, h: [1, 256]
	Strides	w, h: [1, 256]
	Padding	w: [0, min(kernel_w-1,15)] h: [0, min(kernel_h-1,15)]
	Input Size	Arbitrary
	Input Channel	1~256 * channel_parallel
	Output Channel	1~256 * channel_parallel
	Activation	ReLU, ReLU6, LeakyReLU, Hard Sigmoid and Hard Swish
	Dilation	dilation * input_channel ≤ 256 * channel_parallel && stride_w == 1 && stride_h == 1
	Constraint*	kernel_w * kernel_h * (ceil(input_channel / channel_parallel)) <= bank_depth
Transposed Convolution	Kernel Sizes	kernel_w/stride_w: [1, 16] kernel_h/stride_h: [1, 16]
	Strides	kernel_w/stride_w: [1, 16] kernel_h/stride_h: [1, 16]
	Padding	w: [0, kernel_w-1] h: [0, kernel_h-1]
	Input Size	Arbitrary
	Input Channel	1~256 * channel_parallel
	Output Channel	1~256 * channel_parallel
	Activation	ReLU, ReLU6 and LeakyReLU
Depthwise Transposed Convolution	Kernel Sizes	kernel_w/stride_w: [1, 16] kernel_h/stride_h: [1, 16]
	Strides	kernel_w/stride_w: [1, 16] kernel_h/stride_h: [1, 16]
	Padding	w: [0, kernel_w-1] h: [0, kernel_h-1]
	Input Size	Arbitrary
	Input Channel	1~256 * channel_parallel
	Output Channel	1~256 * channel_parallel
	Activation	ReLU, ReLU6, LeakyRelu, Hard Sigmoid and Hard Swish
Max Pooling	Kernel Sizes	w, h: [1, 256]
	Strides	w, h: [1, 256]
	Padding	w: [0, min(kernel_w-1,15)] h: [0, min(kernel_h-1,15)]
Average Pooling	Kernel Sizes	w, h: [1, 256]
	Strides	w, h: [1, 256]
	Padding	w: [0, min(kernel_w-1,15)] h: [0, min(kernel_h-1,15)]
Elementwise-Sum	Input channel	1~256 * channel_parallel
	Input size	Arbitrary
	Feature Map Number	1~4
Elementwise-Multiply	Input channel	1~256 * channel_parallel
	Input size	Arbitrary
	Feature Map Number	2
Concat	Output channel	1~256 * channel_parallel
Reorg	Strides	stride * stride * input_channel ≤ 256 * channel_parallel
Fully Connected	Input_channel	Input_channel ≤ 2048 * channel_parallel
Fully Connected	Output_channel	Arbitrary
The parameter channel_parallel is determined by the DPUCZDX8G configuration. For example, channel_parallel for the B1152 is 12, and channel_parallel for B4096 is 16 (see Parallelism for Different Convolution Architectures table in Configuration Options section). In some neural networks, the FC layer is connected with a Flatten layer. The Vitis AI compiler will automatically combine Flatten+FC to a global CONV2D layer, and the CONV2D kernel size is equal to the input feature map size of Flatten layer. For this case, the input feature map size cannot exceed this automatically configured CONV2D kernel size, otherwise an error will be generated during compilation. If there is no flatten layer, the FC layer will be treated as a normal conv layer. This limitation is present only in cases where the Flatten and FC layers are fused by the compiler. The bank_depth refers to the on-chip weight buffer depth. In all DPU architectures, the bank_depth of the feature map and weights is 2048. If Batch Normalization operators can be transformed by nature of equivalency to depthwise-conv-2d, the operator will be transformed for execution on the DPU. Otherwise, batch_norm will be executed by CPU.

Introduction - Introduction - 4.0 English - PG338

DPUCZDX8G for Zynq UltraScale+ MPSoCs Product Guide (PG338)