Revision History - Revision History - 4.0 English - PG332

Xilinx Embedded RDMA Enabled NIC LogiCORE IP Product Guide (PG332)

Document ID
PG332
Release Date
2022-12-02
Version
4.0 English

The following table shows the revision history for this document.

Date

Version

Revision

12/02/2022

4.0

Updated Features .

Updated Feature Summary .

Updated Table: Invalidate/Immediate Data Entry Structure .

Updated Table: ERNIC Parameters .

Updated Register Space .

Updated This Figure .

Updated Table: ERNIC Registers Details .

Updated Table: Address Space Allocation Requirement for Slave Interfaces .

Updated Table: ERNIC IP Memory Requirement .

06/30/2021

3.1

Updated size to 256 in Table: Address Space Allocation Requirement for Slave Interfaces .

06/16/2021

3.1

Added Versal ACAP.

Added timing violation note in Features .

Updated This Figure .

Added non-RDMA packet description in RX PKT Handler .

Added retransmission description in Response Handler .

Updated maximum DMA length and added Read response descriptions in Unsupported Features .

Updated Table: Decoding for FATAL Codes .

Added description for rx_pkt_hndler_ddr_m_axi* in Table: ERNIC IP Ports .

Updated description for 0x20088, 0x2013C, 0x20200 + ((i-1) x 0x0100), and 0x202B0 + ((i-1) x 0x0100) in Table: ERNIC Registers Details .

Updated size in Table: Address Space Allocation Requirement for Slave Interfaces .

Added QP Fatal Recovery .

Added Requesting ERNIC Support Questionnaire .

02/26/2021

3.0

Updated Resource Utilization link.

01/21/2021

3.0

Updated Priority flow control in Features .

Added Navigating Content by Design Process section.

Added Flow Control Manager in Feature Summary .

Updated This Figure .

Added RDMA READ/WRITE request description in ERNIC RX Path .

Updated This Figure .

Updated CMAC RX/TX descriptions and RoCE descriptions in Table: ERNIC IP Ports .

Updated This Figure .

Updated Table: ERNIC Registers Details .

Updated This Figure .

Updated address for RCV Q Buffer base address QPi (RQBAMSBi).

Updated descriptions #2 and #3 in Complete Dump of the ERNIC Registers .

06/10/2020

2.0

Added new chapter ERNIC Software Flow

12/09/2019

1.0

Updated Table: ERNIC IP Ports and Table: ERNIC IP Memory Requirement .

07/10/2019

1.0

Minor updates

12/05/2018

1.0

Initial Xilinx release.