This section summarizes the estimated maximum performance for various modules within the ERNIC IP. The data is separated into a table per device family. Each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.
• Resource use numbers are taken from the utilization report issued at the end of an implementation using the Out-of-Context flow in Vivado Design Suite.
• The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure. These properties are enabled using the following Tcl command: set_param ips.includeClockLocationConstraints true
• The frequencies used for clock inputs are stated for each test case.
• LUT numbers do not include LUTs used as pack-thrus, but include LUTs used as memory.
• Default Vivado ® Design Suite 2018.1 settings are used. You can improve on these numbers using different settings. However, because the surrounding circuitry will affect placement and timing, these numbers might not repeat in a larger design.
For more details about resource utilization, see the Performance and Resource Utilization .