All the ERNIC registers are synchronous to the AXI4-Lite domain. Any bits not specified in register tables below are considered reserved and return the values as 0 upon read. The power-on reset values of control registers are 0 unless specified in the definition. You should always write the reserved locations with a 0 unless stated otherwise. Only address offsets are listed in the table below and the base address is configured by the AXI interconnect at system level. The contents of the memory region table are used for header validation as shown in the following figure.
|
Address |
Access |
Register Name |
Details |
|---|---|---|---|
|
0x00 + ((i) x 0x0100) Where i=0 to 2047 |
RW |
Protection Domain Number (PDPDNUM) |
Protection Domain Number from the memory region table Width = 24 Default value = 0 |
|
0x04 + ((i) x 0x0100) |
RW |
Virtual address LSB (VIRTADDRLSB) |
This register provides the Virtual Add of the buffer base address LSB. Width = 32 Default value = 0 |
|
0x08 + ((i) x 0x0100) |
RW |
Virtual address MSB (VIRTADDRMSB) |
This register provides the Virtual Add of the buffer base address MSB. Width = 32 Default value = 0 |
|
0x0C + ((i) x 0x0100) |
|
Buffer Base address LSB (BUFBASEADDRLSB) |
This register provides the Write/Read buffer base address MSB. Width = 32 Default value = 0 |
|
0x10 + ((i) x 0x0100) |
RW |
Buffer base address MSB (BUFBASEADDRMSB) |
This register provides the Write/Read buffer base address LSB. Width = 32 Default value = 0 |
|
0x14 + ((i) x 0x0100) |
RW |
Buffer R_Key (BUFRKEY) |
This register provides the Write/Read buffer R_KEY register. Width = 8 Default value = 0 |
|
0x18 + ((i) x 0x0100) |
RW |
Write/Read buffer length (WRRDBUFLEN) |
This register provides the Write/Read buffer length LSB register. Width = 32 Default value = 0 |
|
0x1C + ((i) x 0x0100) |
RW |
Access Description (ACCESSDESC) |
This register provides [7:0] the Access description of the Protection Domain and [31:16] Write/Read buffer length MSB register. Default value is 0. • [3:0]: Access type ° 4'b0000: READ Only ° 4'b0001: Write Only ° 4'b0010: Read and Write ° Other values: Not supported • [15:4]: Reserved • [31:16]: w_r_buf_len_msb. Register provides the Write/Read buffer length [47:32] |
|
0x10_0000 |
RW |
XRNIC Configuration (XRNICCONF) |
This register provides the basic global (not QP specific) configuration controls for the ERNIC IP • [0]: ERNIC Enable • [1]: Reserved • [2]: Reserved • [4:3]: TX ACK generation. ° 00 – (default) ACK only generated on explicit ACK request in the incoming packet or on timeout ° 01 – ACK generated only on timeout ° 10 – ACK generated only on explicit ACK request in the incoming packet • [5]: Error buffer enable. This bit is set to enable the error buffer • [7:6]: Reserved • [23:8]: UDP source port for outgoing packets • [31:24]: Reserved |
|
0x10_0004 |
RW |
XRNIC Advance Configuration (XRNICADCONF) |
This register provides advanced configuration controls for the ERNIC IP. • [0]: SW override enable. Allows SW write access to the following Read Only Registers – CQHEADn, STATCURRSQPTRn, and STATRQPIDBn (where is the QP number) • [1]: Reserved • [2]: retry_cnt_fatal_dis • [15:3]: Reserved • [19:16]: Base count width ° Approximate number of system clocks that make 4096us. ° For 400 MHz clock -->Program decimal 11 ° For 200 MHz clock --> Program decimal 10 ° For 125 MHz clock --> Program decimal 09 ° For 100 MHz clock --> Program decimal 09 ° For N MHz clock ---> Value should be CLOG2(4.096 *N) • [30:20] Software Override QP Number • [31]: Reserved |
|
0x10_0008 |
RW |
XRNIC_BUF_
|
This register provides XON and XOFF Configuration for RoCE Traffic. • [15:0]: XON Value for RoCE • [31:16]: XOFF Value for RoCE Default value = 0x0096005A |
|
0x10_000C |
RW |
XRNIC_PAUSE_CONF |
This register provides PFC configuration. • [0]: Pause enable RoCE • [1]: Pause enable non-RoCE • [7:4]: Pause priority for RoCE (Binary encoding) • [11:8]: Pause priority for non-RoCE (Binary encoding) • [13]: Disable priority check (applicable only for TX data path) Default value = 0x800 |
|
0x10_0010 |
RW |
MAC XRNIC Address LSB (MACXADDLSB) |
This is the MAC Address for local (ERNIC) device and should be configured before the XRNICCONF[0] is set to 1. • [31:0]: MAC local address LSB |
|
0x10_0014 |
RW |
MAC XRNIC Address MSB (MACXADDMSB) |
MAC Address for local (ERNIC) device. Should be configured before the XRNICCONF[0] is set to 1. • [15:0]: MAC local address MSB • [31:16]: Reserved |
|
0x10_0018 |
RW |
XRNIC_BUF_
|
This register provides XON and XOFF configuration for non-RoCE traffic. • [15:0]: XON value for non-RoCE • [31:16]: XOFF value for non-RoCE Default value = 0x0096005A |
|
0x10_0020 |
RW |
IPv6 Address 1 (IPv6XADD1) |
IPv6 address [32:0] for local (ERNIC) device. Should be configured before the XRNICCONF[0] is set to 1. [31:0]: IP address [31:0] |
|
0x10_0024 |
RW |
IPv6 Address 2 (IPv6XADD2) |
IPv6 address [63:32] for local (ERNIC) device. Should be configured before the XRNICCONF[0] is set to 1. [31:0]: IP address [63:32] |
|
0x10_0028 |
RW |
IPv6 Address 3 (IPv6XADD3) |
IPv6 address [95:64] for local (ERNIC) device. Should be configured before the XRNICCONF[0] is set to 1. [31:0]: IP address [95:64] |
|
0x10_002C |
RW |
IPv6 Address 4 (IPv6XADD4) |
IPv6 address [127:96] for local (ERNIC) device. Should be configured before the XRNICCONF[0] is set to 1. [31:0]: IP address [127:96] |
|
0x10_0060 |
RW |
Error Buffer Base Address (ERRBUFBA) |
This register provides the base address for Error buffers. The ERNIC IP updates these buffers with incoming packets that fail validation. The writes to this buffer for all validation errors are enabled by writing a 1 to XRNICCONF[5]. If this bit is disabled, only packets that cause the QP to move to a FATAL state are written to the error buffer. • [31:0]: Error buffer base address LSB 32 bits |
|
0x10_0044 |
RW |
XRNIC_CONF_QP_EN |
This register contains the information about how many QPs are going to be active. • [10:0]: Number of QPs enabled • [31:11]: Reserved |
|
0x10_0064 |
RW |
Error Buffer Base Address msb (ERRBUFBAMSB) |
This register provides the msb base address for Error buffers. • [31:0]: Error buffer base address MSB 32 bits |
|
0x10_0068 |
RW |
Error Buffer Size (ERRBUFSZ) |
This register provides the size of the error buffer • [15:0]: Number of Error buffers • [31:16]: Size of each Error buffer |
|
0x10_006C |
RO |
Error Buffer write pointer (ERRBUFWPTR) |
This register is updated by the ERNIC IP when any error packet is written to the error buffer. The pointer informs the driver of the number of error packets received. • [15:0]: Write pointer doorbell for Error Buffer |
|
0x10_0070 |
RW |
IPv4 XRNIC Address (IPv4XADD) |
IPv4 address for local (ERNIC) device. • [31:0]: IPv4 address |
|
0x10_0078 |
RW |
Outgoing Pkt Error status Queue Base address (OPKTERRQBA) |
This register is used to configure the base address for outgoing packet error status queue. See ERNIC RX Path for details of the outgoing packet error status queue. [31:0]: Outgoing Pkt Error Status Queue base address |
|
0x10_007C |
RW |
Outgoing Pkt Error status Queue Base address (OPKTERRQBAMSB) |
This register is used to configure the msb base address for outgoing packet error status queue. See ERNIC RX Path for details of the outgoing packet error status queue. [63:32]: Outgoing Pkt Error Status Queue base address msb |
|
0x10_0080 |
RW |
Outgoing Error status Q size (OUTERRSTSQSZ) |
[15:0]: Number of entries in outgoing error Q. |
|
0x10_0084 |
RW |
Outgoing Error status Q write pointer Doorbell (OPTERRSTSQQPTRDB) |
Outgoing Error status Q write pointer doorbell. The hardware keeps writing to the buffer in a circular fashion. Does not take care of buffer overflow. Needs to be handled in SW. |
|
0x10_0088 |
RW |
Incoming Pkt Error Status Queue Base address (IPKTERRQBA) |
This register is used to configure the base address for incoming packet error status queue. See ERNIC RX Path for details of the incoming packet error status queue. [31:0]: Incoming Pkt Error Status Queue base address |
|
0x10_008C |
RW |
Incoming Pkt Error Status Queue Base address MSB (IPKTERRQBAMSB) |
This register is used to configure the msb base address for incoming packet error status queue. |
|
0x10_0090 |
RW |
Incoming Pkt Error Status Queue Size (IPKTERRQSZ) |
This register is used to configure the size of the incoming packet error status queue. • [15:0]: Number of incoming error pkt status queue entries • [31:16]: Reserved |
|
0x10_0094 |
RO |
Incoming Pkt Error Status write pointer (IPKTERRQWPTR) |
This status register provides information on the number of incoming error packets received by the ERNIC IP. [15:0]: Write pointer doorbell for incoming error status queue. ERNIC IP writes to the queue in a circular manner without taking care of overflow. This needs to be handled in SW. |
|
0x10_00A0 |
RW |
Data Buffer Base Address (DATBUFBA) |
These data buffers are used by the ERNIC to save all outgoing RDMA WRITE data until it is acknowledged by the remote host. In the event of retransmission, the retried data is pulled from these buffers. [31:0]: Data Buffer base address |
|
0x10_00A4 |
RW |
Data Buffer Base Address MSB (DATBUFBAMSB) |
These data buffers are used by the ERNIC to save all outgoing RDMA WRITE data until it is acknowledged by the remote host. In the event of retransmission, the retried data is pulled from these buffers. [63:32]: Data Buffer base address MSB |
|
0x10_00A8 |
RW |
Data Buffer Size (DATBUFSZ) |
This register is used to configure the size of the data buffers. • [15:0]: Number of data buffers • [31:16]: Data buffer size in bytes |
|
0x10_00AC |
RW |
Connect IP configuration (CON_IO_CONF) |
This register is used to ring the doorbell when hardware handshake is just enabled. • [15:0]: Reserved • [26:16]: Queue pair ID • [30:27]: Reserved • [31]: Connect IO ready indication. This bit is read only and when set to 1'b1 indicates that the connect IO configuration is done and ready to accept for another QPID |
|
0x10_00B0 |
RW |
Response Error pkt buffer base address (RESPERRPKTBA) |
These error buffers are used by the ERNIC to save all error response error packet header information. This register holds the LSB 32 bits of the response error packet buffer [31:0]: Response Error pkt Buffer base address lsb |
|
0x10_00B4 |
RW |
Response Error pkt buffer base address msb (RESPERRPKTBAMSB) |
This register holds the MSB 32 bits of the response error buffer [31:0]: Response Error pkt Buffer base address msb |
|
0x10_00B8 |
RW |
Response Error pkt buffer size address (RESPERRSZ) |
This register provides information of size of each entry and depth of response error buffer [15:0]: Number of entries for response error buffer [31:16]: Size of each entry of response error buffer Note: This register should be programmed to a valid value for proper operation. |
|
0x10_00BC |
RW |
Response Error pkt buffer write pointer (RESPERRWRPTR) |
This register indicate current write pointer of the response error buffer [15:0]: Current write pointer [31:16]: Reserved |
|
Global Status Registers |
|||
|
0x10_0100 |
RO |
Incoming SEND/Read Response Pkt count (INSRRPKTCNT) |
This is a status register which provides information about incoming RDMA SEND and RDMA READ response packets. • [15:0]: Incoming SEND packet count • [31:16]: Incoming Read Response packet count |
|
0x10_0104 |
RO |
Incoming ACK/MAD Pkt count (INAMPKTCNT) |
This is a status register which provides information about incoming acknowledgment and Management Datagram (MAD) packets. • [15:0]: Incoming ACK packet count • [31:16]: Incoming MAD packet count |
|
0x10_0108 |
RO |
Outgoing IO (SEND/READ/WRITE) Pkt count (OUTIOPKTCNT) |
This is a status register which provides information about outgoing RDMA SEND and RDMA READ/WRITE packets. • [15:0]: Outgoing SEND packet count • [31:16]: Outgoing RDMA READ/WRITE packet count |
|
0x10_010C |
RO |
Outgoing ACK/MAD Pkt count (OUTAMPKTCNT) |
This is a status register which provides information about outgoing acknowledgment and MAD packets. • [15:0]: Outgoing ACK packet count • [31:16]: Outgoing MAD packet count |
|
0x10_0110 |
RO |
Last incoming pkt (LSTINPKT) |
This status register provides details of the last incoming packet received. • [7:0]: Opcode of the last incoming packet • [19:8]: PSN LSB bits of the last incoming packet • [30:20]: QPID of the last incoming packet • [31]: Reserved |
|
0x10_0114 |
RO |
Last outgoing pkt (LSTOUTPKT) |
This status register provides the details of the last outgoing packet. • [7:0]: Opcode of the last outgoing packet • [19:8]: PSN LSB bits of the last outgoing packet • [30:20]: QPID of the last outgoing packet • [31]: Reserved |
|
0x10_0118 |
RO |
Incoming Invalid/Duplicate pkt count (ININVDUPCNT) |
This status register provides information on incoming invalid or duplicate packets. • [15:0]: Incoming Invalid packet count • [31:16]: Incoming Duplicate packet count |
|
0x10_0124 |
RO |
WQE Processor Status (WQEPROCSTS) |
This status register provides the status of WQE processor engine and is used for debug purposes. • [2:0]: WQE processor state • [3]: reserved • [4]: retry buffers unavailable • [5]: internal FIFO empty status • [6]: Buffer manager busy signal • [11:7]: reserved • [12]: Back pressure indication from CMAC. Sticky bit • [15:12]: Header buffer manager FSM state • [23:16]: Buffer tail pointer • [31:24]: Buffer head pointer |
|
0x10_012C |
RO |
QP Manager Status (QPMSTS) |
This status register provides the status of QP manager and is used for debug purposes. • [0]: WQE Cache full • [1]: WQE Cache empty • [15:2]: Reserved • [31:16]: Count of WQEs processed |
|
0x10_0130 |
RO |
Incoming all/dropped pkt count (INALLDRPPKTCNT) |
This status register is provides details of all incoming and dropped packets. • [15:0]: Incoming dropped packet count • [31:16]: All incoming packet count |
|
0x10_0134 |
RO |
Incoming NAK pkt count (INNAKPKTCNT) |
This status register is provides details of all incoming NAK packets. • [15:0]: Incoming NAK packet count • [31:16]: Reserved |
|
0x10_0138 |
RO |
Outgoing NAK pkt count (OUTNAKPKTCNT) |
This status register is provides details of all outgoing NAK packets. • [15:0]: Outgoing NAK packet count • [31:16]: Reserved |
|
0x10_013C |
RO |
Response handler Status (RESPHNDSTS) |
This status register provides the status of Response Handler module and is used for debug purposes. • [10:0]: Arbitrated QP Index • [16:11]: Response handler FSM state • [17]: Acks to process • [31:18]: Reserved |
|
0x10_0140 |
RO |
Retry count status (RETRYCNTSTS) |
This status register provides details of retransmitted packets. [31:0] Retry count |
|
0x10_0174 |
RO |
Incoming CNP packet count (INCNPPKTCNT) |
Incoming CNP packet count |
|
0x10_0178 |
RO |
Outgoing CNP packet count (OUTCNPPKTCNT) |
Outgoing CNP packet count |
|
0x10_017C |
RO |
Outgoing read response packet count (OUTRDRSPPKTCNT) |
Outgoing read response packet count |
|
0x10_0180 |
RW |
Interrupt Enable (INTEN) |
This register provides the configuration control for interrupts generated by the ERNIC IP. • [0]: Incoming packet validation error interrupt enable • [1]: Incoming MAD packet received interrupt enable • [2]: Reserved • [3]: RNR NACK generated interrupt enable • [4]: WQE completion interrupt enable (asserted for QPs for which QPCONF[3] bit is set) • [5]: Illegal opcode posted in SEND Queue interrupt enable • [6]: RQ Packet received interrupt enable (asserted for QPs for which QPCONF[2] bit is set • [7]: Fatal error received interrupt enable • [8]: Interrupt enable for CNP scheduling |
|
0x10_0184 |
W1C |
Interrupt Status (INTSTS) |
This status register provides the cause of an asserted interrupt. • [0]: Incoming packet validation error interrupt • [1]: Incoming MAD packet received interrupt • [2]: Reserved • [3]: RNR NACK generated interrupt • [4]: WQE completion interrupt (asserted for QPs for which QPCONF[3] bit is set) • [5]: Illegal opcode posted in SEND Queue interrupt • [6]: RQ Packet received interrupt (asserted for QPs for which QPCONF[2] bit is set) • [7]: Fatal error received interrupt • [8]: Interrupt enable for CNP scheduling |
|
0x10_0190 |
WC1 |
RCV Q interrupt status (bitwise) QP 0-31 (RQINTSTS1) |
This register provides the RQ interrupt status for QPs 0 to 31. Bit [i] provides the interrupt status for RQi where i=0 to 31. [i]: Interrupt status for RQ i |
|
0x10_0194 |
WC1 |
RCV Q interrupt status (bitwise) QP 32-63 (RQINTSTS2) |
This register provides the RQ interrupt status for QPs 32 to 63. Bit [i] provides the interrupt status for RQ(i+32) where i=0 to 31. [i]: Interrupt status for RQ(i+32) |
|
0x10_0198 |
WC1 |
RCV Q interrupt status (bitwise) QP 64-95 (RQINTSTS3) |
This register provides the RQ interrupt status for QPs 64 to 95. Bit [i] provides the interrupt status for RQ(i+64) where i=0 to 31. [i]: Interrupt status for RQ(i+64) |
|
0x10_019C |
WC1 |
RCV Q interrupt status (bitwise) QP 96-127 (RQINTSTS4) |
This register provides the RQ interrupt status for QPs 96 to 127. Bit [i] provides the interrupt status for RQ(i+96) where i=0 to 31. [i]: Interrupt status for RQ(i+96) |
|
0x10_01A0 |
WC1 |
RCV Q interrupt status (bitwise) QP 128-159 (RQINTSTS5) |
This register provides the RQ interrupt status for QPs 128 to 159. Bit [i] provides the interrupt status for RQ(i+128) where i=0 to 31. [i]: Interrupt status for RQ(i+128) |
|
0x10_01A4 |
WC1 |
RCV Q interrupt status (bitwise) QP 160-191 (RQINTSTS6) |
This register provides the RQ interrupt status for QPs 160 to 191. Bit [i] provides the interrupt status for RQ(i+160) where i=0 to 31. [i]: Interrupt status for RQ(i+160) |
|
0x10_01A8 |
WC1 |
RCV Q interrupt status (bitwise) QP 192-223 (RQINTSTS7) |
This register provides the RQ interrupt status for QPs 192 to 223. Bit [i] provides the interrupt status for RQ(i+192) where i=0 to 31. [i]: Interrupt status for RQ(i+192) |
|
0x10_01AC |
WC1 |
RCV Q interrupt status (bitwise) QP 224-255 (RQINTSTS8) |
This register provides the RQ interrupt status for QPs 224 to 255. Bit [i] provides the interrupt status for RQ(i+224) where i=0 to 31. [i]: Interrupt status for RQ(i+224) |
|
0x10_01B0 |
WC1 |
RCV Q interrupt status (bitwise) QP 256-287 (RQINTSTS9) |
This register provides the RQ interrupt status for QPs 256 to 287. Bit [i] provides the interrupt status for RQ(i+256) where i=0 to 31.[i]: Interrupt status for RQ(i+256) |
|
0x10_01B4 |
WC1 |
RCV Q interrupt status (bitwise) QP 288-319 (RQINTSTS10) |
This register provides the RQ interrupt status for QPs 288 to 319. Bit [i] provides the interrupt status for RQ(i+288) where i=0 to 31.[i]: Interrupt status for RQ(i+288) |
|
0x10_01B8 |
WC1 |
RCV Q interrupt status (bitwise) QP 320-351 (RQINTSTS11) |
This register provides the RQ interrupt status for QPs 320 to 351. Bit [i] provides the interrupt status for RQ(i+320) where i=0 to 31.[i]: Interrupt status for RQ(i+320) |
|
0x10_01BC |
WC1 |
RCV Q interrupt status (bitwise) QP 352-383 (RQINTSTS12) |
This register provides the RQ interrupt status for QPs 352 to 383. Bit [i] provides the interrupt status for RQ(i+352) where i=0 to 31.[i]: Interrupt status for RQ(i+352) |
|
0x10_01C0 |
WC1 |
RCV Q interrupt status (bitwise) QP 384-415 (RQINTSTS13) |
This register provides the RQ interrupt status for QPs 384 to 415. Bit [i] provides the interrupt status for RQ(i+384) where i=0 to 31.[i]: Interrupt status for RQ(i+384) |
|
0x10_01C4 |
WC1 |
RCV Q interrupt status (bitwise) QP 416-447 (RQINTSTS14) |
This register provides the RQ interrupt status for QPs 416 to 447. Bit [i] provides the interrupt status for RQ(i+416) where i=0 to 31.[i]: Interrupt status for RQ(i+416) |
|
0x10_01C8 |
WC1 |
RCV Q interrupt status (bitwise) QP 448-479 (RQINTSTS15) |
This register provides the RQ interrupt status for QPs 448 to 479. Bit [i] provides the interrupt status for RQ(i+448) where i=0 to 31.[i]: Interrupt status for RQ(i+448) |
|
0x10_01CC |
WC1 |
RCV Q interrupt status (bitwise) QP 480-511 (RQINTSTS16) |
This register provides the RQ interrupt status for QPs 480 to 511. Bit [i] provides the interrupt status for RQ(i+480) where i=0 to 31.[i]: Interrupt status for RQ(i+480) |
|
0x10_01D0 |
WC1 |
RCV Q interrupt status (bitwise) QP 512-543 (RQINTSTS17) |
This register provides the RQ interrupt status for QPs 512 to 543. Bit [i] provides the interrupt status for RQ(i+512) where i=0 to 31.[i]: Interrupt status for RQ(i+512) |
|
0x10_01D4 |
WC1 |
RCV Q interrupt status (bitwise) QP 544-575 (RQINTSTS18) |
This register provides the RQ interrupt status for QPs 544 to 575. Bit [i] provides the interrupt status for RQ(i+544) where i=0 to 31.[i]: Interrupt status for RQ(i+544) |
|
0x10_01D8 |
WC1 |
RCV Q interrupt status (bitwise) QP 576-607 (RQINTSTS19) |
This register provides the RQ interrupt status for QPs 576 to 607. Bit [i] provides the interrupt status for RQ(i+576) where i=0 to 31.[i]: Interrupt status for RQ(i+576) |
|
0x10_01DC |
WC1 |
RCV Q interrupt status (bitwise) QP 608-639 (RQINTSTS20) |
This register provides the RQ interrupt status for QPs 608 to 639. Bit [i] provides the interrupt status for RQ(i+608) where i=0 to 31.[i]: Interrupt status for RQ(i+608) |
|
0x10_01E0 |
WC1 |
RCV Q interrupt status (bitwise) QP 640-671 (RQINTSTS21) |
This register provides the RQ interrupt status for QPs 640 to 671. Bit [i] provides the interrupt status for RQ(i+640) where i=0 to 31.[i]: Interrupt status for RQ(i+640) |
|
0x10_01E4 |
WC1 |
RCV Q interrupt status (bitwise) QP 672-703 (RQINTSTS22) |
This register provides the RQ interrupt status for QPs 672 to 703. Bit [i] provides the interrupt status for RQ(i+672) where i=0 to 31.[i]: Interrupt status for RQ(i+672) |
|
0x10_01E8 |
WC1 |
RCV Q interrupt status (bitwise) QP 704-735 (RQINTSTS23) |
This register provides the RQ interrupt status for QPs 704 to 735. Bit [i] provides the interrupt status for RQ(i+704) where i=0 to 31.[i]: Interrupt status for RQ(i+704) |
|
0x10_01EC |
WC1 |
RCV Q interrupt status (bitwise) QP 736-767 (RQINTSTS24) |
This register provides the RQ interrupt status for QPs 736 to 767. Bit [i] provides the interrupt status for RQ(i+736) where i=0 to 31.[i]: Interrupt status for RQ(i+736) |
|
0x10_01F0 |
WC1 |
RCV Q interrupt status (bitwise) QP 768-799 (RQINTSTS25) |
This register provides the RQ interrupt status for QPs 768 to 799. Bit [i] provides the interrupt status for RQ(i+768) where i=0 to 31.[i]: Interrupt status for RQ(i+768) |
|
0x10_01F4 |
WC1 |
RCV Q interrupt status (bitwise) QP 800-831 (RQINTSTS26) |
This register provides the RQ interrupt status for QPs 800 to 831. Bit [i] provides the interrupt status for RQ(i+800) where i=0 to 31.[i]: Interrupt status for RQ(i+800) |
|
0x10_01F8 |
WC1 |
RCV Q interrupt status (bitwise) QP 832-863 (RQINTSTS27) |
This register provides the RQ interrupt status for QPs 832 to 863. Bit [i] provides the interrupt status for RQ(i+832) where i=0 to 31.[i]: Interrupt status for RQ(i+832) |
|
0x10_01FC |
WC1 |
RCV Q interrupt status (bitwise) QP 864-895 (RQINTSTS28) |
This register provides the RQ interrupt status for QPs 864 to 895. Bit [i] provides the interrupt status for RQ(i+864) where i=0 to 31.[i]: Interrupt status for RQ(i+864) |
|
0x10_0200 |
WC1 |
RCV Q interrupt status (bitwise) QP 896-927 (RQINTSTS29) |
This register provides the RQ interrupt status for QPs 896 to 927. Bit [i] provides the interrupt status for RQ(i+896) where i=0 to 31.[i]: Interrupt status for RQ(i+896) |
|
0x10_0204 |
WC1 |
RCV Q interrupt status (bitwise) QP 928-949 (RQINTSTS30) |
This register provides the RQ interrupt status for QPs 928 to 949. Bit [i] provides the interrupt status for RQ(i+928) where i=0 to 31.[i]: Interrupt status for RQ(i+928) |
|
0x10_0208 |
WC1 |
RCV Q interrupt status (bitwise) QP 960-991 (RQINTSTS31) |
This register provides the RQ interrupt status for QPs 960 to 991. Bit [i] provides the interrupt status for RQ(i+960) where i=0 to 31.[i]: Interrupt status for RQ(i+960) |
|
0x10_020C |
WC1 |
RCV Q interrupt status (bitwise) QP 992-1023 (RQINTSTS32) |
This register provides the RQ interrupt status for QPs 992 to 1023. Bit [i] provides the interrupt status for RQ(i+992) where i=0 to 31.[i]: Interrupt status for RQ(i+992) |
|
0x10_0210 |
WC1 |
RCV Q interrupt status (bitwise) QP 1024-1055 (RQINTSTS33) |
This register provides the RQ interrupt status for QPs 1024 to 1055. Bit [i] provides the interrupt status for RQ(i+1024) where i=0 to 31.[i]: Interrupt status for RQ(i+1024) |
|
0x10_0214 |
WC1 |
RCV Q interrupt status (bitwise) QP 1056-1087 (RQINTSTS34) |
This register provides the RQ interrupt status for QPs 1056 to 1087. Bit [i] provides the interrupt status for RQ(i+1056) where i=0 to 31.[i]: Interrupt status for RQ(i+1056) |
|
0x10_0218 |
WC1 |
RCV Q interrupt status (bitwise) QP 1088-1119 (RQINTSTS35) |
This register provides the RQ interrupt status for QPs 1088 to 1119. Bit [i] provides the interrupt status for RQ(i+1088) where i=0 to 31.[i]: Interrupt status for RQ(i+1088) |
|
0x10_021C |
WC1 |
RCV Q interrupt status (bitwise) QP 1120-1151 (RQINTSTS36) |
This register provides the RQ interrupt status for QPs 1120 to 1151. Bit [i] provides the interrupt status for RQ(i+1120) where i=0 to 31.[i]: Interrupt status for RQ(i+1120) |
|
0x10_0220 |
WC1 |
RCV Q interrupt status (bitwise) QP 1152-1183 (RQINTSTS37) |
This register provides the RQ interrupt status for QPs 1152 to 1183. Bit [i] provides the interrupt status for RQ(i+1152) where i=0 to 31.[i]: Interrupt status for RQ(i+1152) |
|
0x10_0224 |
WC1 |
RCV Q interrupt status (bitwise) QP 1184-1215 (RQINTSTS38) |
This register provides the RQ interrupt status for QPs 1184 to 1215. Bit [i] provides the interrupt status for RQ(i+1184) where i=0 to 31.[i]: Interrupt status for RQ(i+1184) |
|
0x10_0228 |
WC1 |
RCV Q interrupt status (bitwise) QP 1216-1247 (RQINTSTS39) |
This register provides the RQ interrupt status for QPs 1216 to 1247. Bit [i] provides the interrupt status for RQ(i+1216) where i=0 to 31.[i]: Interrupt status for RQ(i+1216) |
|
0x10_022C |
WC1 |
RCV Q interrupt status (bitwise) QP 1248-1279 (RQINTSTS40) |
This register provides the RQ interrupt status for QPs 1248 to 1279. Bit [i] provides the interrupt status for RQ(i+1248) where i=0 to 31.[i]: Interrupt status for RQ(i+1248) |
|
0x10_0230 |
WC1 |
RCV Q interrupt status (bitwise) QP 1280-1311 (RQINTSTS41) |
This register provides the RQ interrupt status for QPs 1280 to 1311. Bit [i] provides the interrupt status for RQ(i+1280) where i=0 to 31.[i]: Interrupt status for RQ(i+1280) |
|
0x10_0234 |
WC1 |
RCV Q interrupt status (bitwise) QP 1312-1343 (RQINTSTS42) |
This register provides the RQ interrupt status for QPs 1312 to 1343. Bit [i] provides the interrupt status for RQ(i+1312) where i=0 to 31.[i]: Interrupt status for RQ(i+1312) |
|
0x10_0238 |
WC1 |
RCV Q interrupt status (bitwise) QP 1344-1375 (RQINTSTS43) |
This register provides the RQ interrupt status for QPs 1344 to 1375. Bit [i] provides the interrupt status for RQ(i+1344) where i=0 to 31.[i]: Interrupt status for RQ(i+1344) |
|
0x10_023C |
WC1 |
RCV Q interrupt status (bitwise) QP 1376-1407 (RQINTSTS44) |
This register provides the RQ interrupt status for QPs 1376 to 1407. Bit [i] provides the interrupt status for RQ(i+1376) where i=0 to 31.[i]: Interrupt status for RQ(i+1376) |
|
0x10_0240 |
WC1 |
RCV Q interrupt status (bitwise) QP 1408-1439 (RQINTSTS45) |
This register provides the RQ interrupt status for QPs 1408 to 1439. Bit [i] provides the interrupt status for RQ(i+1408) where i=0 to 31.[i]: Interrupt status for RQ(i+1408) |
|
0x10_0244 |
WC1 |
RCV Q interrupt status (bitwise) QP 1440-1471 (RQINTSTS46) |
This register provides the RQ interrupt status for QPs 1440 to 1471. Bit [i] provides the interrupt status for RQ(i+1440) where i=0 to 31.[i]: Interrupt status for RQ(i+1440) |
|
0x10_0248 |
WC1 |
RCV Q interrupt status (bitwise) QP 1472-1503 (RQINTSTS47) |
This register provides the RQ interrupt status for QPs 1472 to 1503. Bit [i] provides the interrupt status for RQ(i+1472) where i=0 to 31.[i]: Interrupt status for RQ(i+1472) |
|
0x10_024C |
WC1 |
RCV Q interrupt status (bitwise) QP 1504-1535 (RQINTSTS48) |
This register provides the RQ interrupt status for QPs 1504 to 1535. Bit [i] provides the interrupt status for RQ(i+1504) where i=0 to 31.[i]: Interrupt status for RQ(i+1504) |
|
0x10_0250 |
WC1 |
RCV Q interrupt status (bitwise) QP 1536-1567 (RQINTSTS49) |
This register provides the RQ interrupt status for QPs 1536 to 1567. Bit [i] provides the interrupt status for RQ(i+1536) where i=0 to 31.[i]: Interrupt status for RQ(i+1536) |
|
0x10_0254 |
WC1 |
RCV Q interrupt status (bitwise) QP 1568-1599 (RQINTSTS50) |
This register provides the RQ interrupt status for QPs 1568 to 1599. Bit [i] provides the interrupt status for RQ(i+1568) where i=0 to 31.[i]: Interrupt status for RQ(i+1568) |
|
0x10_0258 |
WC1 |
RCV Q interrupt status (bitwise) QP 1600-1631 (RQINTSTS51) |
This register provides the RQ interrupt status for QPs 1600 to 1632. Bit [i] provides the interrupt status for RQ(i+1600) where i=0 to 31.[i]: Interrupt status for RQ(i+1600) |
|
0x10_025C |
WC1 |
RCV Q interrupt status (bitwise) QP 1632-1663 (RQINTSTS52) |
This register provides the RQ interrupt status for QPs 1632 to 1663. Bit [i] provides the interrupt status for RQ(i+1632) where i=0 to 31.[i]: Interrupt status for RQ(i+1632) |
|
0x10_0260 |
WC1 |
RCV Q interrupt status (bitwise) QP 1664-1695 (RQINTSTS53) |
This register provides the RQ interrupt status for QPs 1664 to 1695. Bit [i] provides the interrupt status for RQ(i+1664) where i=0 to 31.[i]: Interrupt status for RQ(i+1664) |
|
0x10_0264 |
WC1 |
RCV Q interrupt status (bitwise) QP 1696-1727 (RQINTSTS54) |
This register provides the RQ interrupt status for QPs 1696 to 1727. Bit [i] provides the interrupt status for RQ(i+1696) where i=0 to 31.[i]: Interrupt status for RQ(i+1696) |
|
0x10_0268 |
WC1 |
RCV Q interrupt status (bitwise) QP 1728-1759 (RQINTSTS55) |
This register provides the RQ interrupt status for QPs 1728 to 1759. Bit [i] provides the interrupt status for RQ(i+1728) where i=0 to 31.[i]: Interrupt status for RQ(i+1728) |
|
0x10_026C |
WC1 |
RCV Q interrupt status (bitwise) QP 1760-1791 (RQINTSTS56) |
This register provides the RQ interrupt status for QPs 1760 to 1791. Bit [i] provides the interrupt status for RQ(i+1760) where i=0 to 31.[i]: Interrupt status for RQ(i+1760) |
|
0x10_0270 |
WC1 |
RCV Q interrupt status (bitwise) QP 1792-1823 (RQINTSTS57) |
This register provides the RQ interrupt status for QPs 1792 to 1823. Bit [i] provides the interrupt status for RQ(i+1792) where i=0 to 31.[i]: Interrupt status for RQ(i+1792) |
|
0x10_0274 |
WC1 |
RCV Q interrupt status (bitwise) QP 1824-1855 (RQINTSTS58) |
This register provides the RQ interrupt status for QPs 1824 to 1855. Bit [i] provides the interrupt status for RQ(i+1824) where i=0 to 31.[i]: Interrupt status for RQ(i+1824) |
|
0x10_0278 |
WC1 |
RCV Q interrupt status (bitwise) QP 1856-1887 (RQINTSTS59) |
This register provides the RQ interrupt status for QPs 1856 to 1887. Bit [i] provides the interrupt status for RQ(i+1856) where i=0 to 31.[i]: Interrupt status for RQ(i+1856) |
|
0x10_027C |
WC1 |
RCV Q interrupt status (bitwise) QP 1888-1919 (RQINTSTS60) |
This register provides the RQ interrupt status for QPs 1888 to 1919. Bit [i] provides the interrupt status for RQ(i+1888) where i=0 to 31.[i]: Interrupt status for RQ(i+1888) |
|
0x10_0280 |
WC1 |
RCV Q interrupt status (bitwise) QP 1920-1951 (RQINTSTS61) |
This register provides the RQ interrupt status for QPs 1920 to 1951. Bit [i] provides the interrupt status for RQ(i+1920) where i=0 to 31.[i]: Interrupt status for RQ(i+1920) |
|
0x10_0284 |
WC1 |
RCV Q interrupt status (bitwise) QP 1952-1983 (RQINTSTS62) |
This register provides the RQ interrupt status for QPs 1952 to 1983. Bit [i] provides the interrupt status for RQ(i+1952) where i=0 to 31.[i]: Interrupt status for RQ(i+1952) |
|
0x10_0288 |
WC1 |
RCV Q interrupt status (bitwise) QP 1984-2015 (RQINTSTS63) |
This register provides the RQ interrupt status for QPs 1984 to 2016. Bit [i] provides the interrupt status for RQ(i+1984) where i=0 to 31.[i]: Interrupt status for RQ(i+1984) |
|
0x10_028C |
WC1 |
RCV Q interrupt status (bitwise) QP 2016-2047 (RQINTSTS64) |
This register provides the RQ interrupt status for QPs 2016 to 2047. Bit [i] provides the interrupt status for RQ(i+2016) where i=0 to 31.[i]: Interrupt status for RQ(i+2016) |
|
0x10_0290 |
WC1 |
Completion Q interrupt status (bitwise) QP 0-31 (CQINTSTS1) |
This register provides the CQ interrupt status for QPs 0 to 31. Bit [i] provides the interrupt status for CQi where i=0 to 31.[i]: Interrupt status for CQ i |
|
0x10_0294 |
WC1 |
Completion Q interrupt status (bitwise) QP 32-63 (CQINTSTS2) |
This register provides the CQ interrupt status for QPs 32 to 63. Bit [i] provides the interrupt status for CQ(i+32) where i=0 to 31.[i]: Interrupt status for CQ(i+32) |
|
0x10_0298 |
WC1 |
Completion Q interrupt status (bitwise) QP 64-95 (CQINTSTS3) |
This register provides the CQ interrupt status for QPs 64 to 95. Bit [i] provides the interrupt status for CQ(i+64) where i=0 to 31.[i]: Interrupt status for CQ(i+64) |
|
0x10_029C |
WC1 |
Completion Q interrupt status (bitwise) QP 96-127 (CQINTSTS4) |
This register provides the CQ interrupt status for QPs 96 to 127. Bit [i] provides the interrupt status for CQ(i+92) where i=0 to 31.[i]: Interrupt status for CQ(i+92) |
|
0x10_02A0 |
WC1 |
Completion Q interrupt status (bitwise) QP 128-159 (CQINTSTS5) |
This register provides the CQ interrupt status for QPs 128 to 159. Bit [i] provides the interrupt status for CQ(i+128) where i=0 to 31.[i]: Interrupt status for CQ(i+128) |
|
0x10_02A4 |
WC1 |
Completion Q interrupt status (bitwise) QP 160-191 (CQINTSTS6) |
This register provides the CQ interrupt status for QPs 160 to 191. Bit [i] provides the interrupt status for CQ(i+160) where i=0 to 31.[i]: Interrupt status for CQ(i+160) |
|
0x10_02A8 |
WC1 |
Completion Q interrupt status (bitwise) QP 192-223 (CQINTSTS7) |
This register provides the CQ interrupt status for QPs 192 to 223. Bit [i] provides the interrupt status for CQ(i+192) where i=0 to 31.[i]: Interrupt status for CQ(i+192) |
|
0x10_02AC |
WC1 |
Completion Q interrupt status (bitwise) QP 224-255 (CQINTSTS8) |
This register provides the CQ interrupt status for QPs 224 to 255. Bit [i] provides the interrupt status for CQ(i+224) where i=0 to 31.[i]: Interrupt status for CQ(i+224) |
|
0x10_02B0 |
WC1 |
Completion Q interrupt status (bitwise) QP 256-287 (CQINTSTS9) |
This register provides the CQ interrupt status for QPs 256 to 287. Bit [i] provides the interrupt status for CQ(i+256) where i=0 to 31.[i]: Interrupt status for CQ(i+256) |
|
0x10_02B4 |
WC1 |
Completion Q interrupt status (bitwise) QP 288-319 (CQINTSTS10) |
This register provides the CQ interrupt status for QPs 288 to 319. Bit [i] provides the interrupt status for CQ(i+288) where i=0 to 31.[i]: Interrupt status for CQ(i+288) |
|
0x10_02B8 |
WC1 |
Completion Q interrupt status (bitwise) QP 320-351 (CQINTSTS11) |
This register provides the CQ interrupt status for QPs 320 to 351. Bit [i] provides the interrupt status for CQ(i+320) where i=0 to 31.[i]: Interrupt status for CQ(i+320) |
|
0x10_02BC |
WC1 |
Completion Q interrupt status (bitwise) QP 352-383 (CQINTSTS12) |
This register provides the CQ interrupt status for QPs 352 to 383. Bit [i] provides the interrupt status for CQ(i+352) where i=0 to 31.[i]: Interrupt status for CQ(i+352) |
|
0x10_02C0 |
WC1 |
Completion Q interrupt status (bitwise) QP 384-415 (CQINTSTS13) |
This register provides the CQ interrupt status for QPs 384 to 415. Bit [i] provides the interrupt status for CQ(i+384) where i=0 to 31.[i]: Interrupt status for CQ(i+384) |
|
0x10_02C4 |
WC1 |
Completion Q interrupt status (bitwise) QP 416-447 (CQINTSTS14) |
This register provides the CQ interrupt status for QPs 416 to 447. Bit [i] provides the interrupt status for CQ(i+416) where i=0 to 31.[i]: Interrupt status for CQ(i+416) |
|
0x10_02C8 |
WC1 |
Completion Q interrupt status (bitwise) QP 448-479 (CQINTSTS15) |
This register provides the CQ interrupt status for QPs 448 to 479. Bit [i] provides the interrupt status for CQ(i+448) where i=0 to 31.[i]: Interrupt status for CQ(i+448) |
|
0x10_02CC |
WC1 |
Completion Q interrupt status (bitwise) QP 480-511 (CQINTSTS16) |
This register provides the CQ interrupt status for QPs 480 to 511. Bit [i] provides the interrupt status for CQ(i+480) where i=0 to 31.[i]: Interrupt status for CQ(i+480) |
|
0x10_02D0 |
WC1 |
Completion Q interrupt status (bitwise) QP 512-543 (CQINTSTS17) |
This register provides the CQ interrupt status for QPs 512 to 543. Bit [i] provides the interrupt status for CQ(i+512) where i=0 to 31.[i]: Interrupt status for CQ(i+512) |
|
0x10_02D4 |
WC1 |
Completion Q interrupt status (bitwise) QP 544-575 (CQINTSTS18) |
This register provides the CQ interrupt status for QPs 544 to 575. Bit [i] provides the interrupt status for CQ(i+544) where i=0 to 31.[i]: Interrupt status for CQ(i+544) |
|
0x10_02D8 |
WC1 |
Completion Q interrupt status (bitwise) QP 576-607 (CQINTSTS19) |
This register provides the CQ interrupt status for QPs 576 to 607. Bit [i] provides the interrupt status for CQ(i+576) where i=0 to 31.[i]: Interrupt status for CQ(i+576) |
|
0x10_02DC |
WC1 |
Completion Q interrupt status (bitwise) QP 608-639 (CQINTSTS20) |
This register provides the CQ interrupt status for QPs 608 to 639. Bit [i] provides the interrupt status for CQ(i+608) where i=0 to 31.[i]: Interrupt status for CQ(i+608) |
|
0x10_02E0 |
WC1 |
Completion Q interrupt status (bitwise) QP 640-671 (CQINTSTS21) |
This register provides the CQ interrupt status for QPs 640 to 671. Bit [i] provides the interrupt status for CQ(i+640) where i=0 to 31.[i]: Interrupt status for CQ(i+640) |
|
0x10_02E4 |
WC1 |
Completion Q interrupt status (bitwise) QP 672-703 (CQINTSTS22) |
This register provides the CQ interrupt status for QPs 672 to 703. Bit [i] provides the interrupt status for CQ(i+672) where i=0 to 31.[i]: Interrupt status for CQ(i+672) |
|
0x10_02E8 |
WC1 |
Completion Q interrupt status (bitwise) QP 704-735 (CQINTSTS23) |
This register provides the CQ interrupt status for QPs 704 to 735. Bit [i] provides the interrupt status for CQ(i+704) where i=0 to 31.[i]: Interrupt status for CQ(i+704) |
|
0x10_02EC |
WC1 |
Completion Q interrupt status (bitwise) QP 736-767 (CQINTSTS24) |
This register provides the CQ interrupt status for QPs 736 to 767. Bit [i] provides the interrupt status for CQ(i+736) where i=0 to 31.[i]: Interrupt status for CQ(i+736) |
|
0x10_02F0 |
WC1 |
Completion Q interrupt status (bitwise) QP 768-799 (CQINTSTS25) |
This register provides the CQ interrupt status for QPs 768 to 799. Bit [i] provides the interrupt status for CQ(i+768) where i=0 to 31.[i]: Interrupt status for CQ(i+768) |
|
0x10_02F4 |
WC1 |
Completion Q interrupt status (bitwise) QP 800-831 (CQINTSTS26) |
This register provides the CQ interrupt status for QPs 800 to 831. Bit [i] provides the interrupt status for CQ(i+800) where i=0 to 31.[i]: Interrupt status for CQ(i+800) |
|
0x10_02F8 |
WC1 |
Completion Q interrupt status (bitwise) QP 832-863 (CQINTSTS27) |
This register provides the CQ interrupt status for QPs 832 to 863. Bit [i] provides the interrupt status for CQ(i+832) where i=0 to 31.[i]: Interrupt status for CQ(i+832) |
|
0x10_02FC |
WC1 |
Completion Q interrupt status (bitwise) QP 864-895 (CQINTSTS28) |
This register provides the CQ interrupt status for QPs 864 to 895. Bit [i] provides the interrupt status for CQ(i+864) where i=0 to 31.[i]: Interrupt status for CQ(i+864) |
|
0x10_0300 |
WC1 |
Completion Q interrupt status (bitwise) QP 896-927 (CQINTSTS29) |
This register provides the CQ interrupt status for QPs 896 to 927. Bit [i] provides the interrupt status for CQ(i+896) where i=0 to 31.[i]: Interrupt status for CQ(i+896) |
|
0x10_0304 |
WC1 |
Completion Q interrupt status (bitwise) QP 928-949 (CQINTSTS30) |
This register provides the CQ interrupt status for QPs 928 to 949. Bit [i] provides the interrupt status for CQ(i+928) where i=0 to 31.[i]: Interrupt status for CQ(i+928) |
|
0x10_0308 |
WC1 |
Completion Q interrupt status (bitwise) QP 960-991 (CQINTSTS31) |
This register provides the CQ interrupt status for QPs 960 to 991. Bit [i] provides the interrupt status for CQ(i+960) where i=0 to 31.[i]: Interrupt status for CQ(i+960) |
|
0x10_030C |
WC1 |
Completion Q interrupt status (bitwise) QP 992-1023 (CQINTSTS32) |
This register provides the CQ interrupt status for QPs 992 to 1023. Bit [i] provides the interrupt status for CQ(i+992) where i=0 to 31.[i]: Interrupt status for CQ(i+992) |
|
0x10_0310 |
WC1 |
Completion Q interrupt status (bitwise) QP 1024-1055 (CQINTSTS33) |
This register provides the CQ interrupt status for QPs 1024 to 1055. Bit [i] provides the interrupt status for CQ(i+1024) where i=0 to 31.[i]: Interrupt status for CQ(i+1024) |
|
0x10_0314 |
WC1 |
Completion Q interrupt status (bitwise) QP 1056-1087 (CQINTSTS34) |
This register provides the CQ interrupt status for QPs 1056 to 1087. Bit [i] provides the interrupt status for CQ(i+1056) where i=0 to 31.[i]: Interrupt status for CQ(i+1056) |
|
0x10_0318 |
WC1 |
Completion Q interrupt status (bitwise) QP 1088-1119 (CQINTSTS35) |
This register provides the CQ interrupt status for QPs 1088 to 1119. Bit [i] provides the interrupt status for CQ(i+1088) where i=0 to 31.[i]: Interrupt status for CQ(i+1088) |
|
0x10_031C |
WC1 |
Completion Q interrupt status (bitwise) QP 1120-1151 (CQINTSTS36) |
This register provides the CQ interrupt status for QPs 1120 to 1151. Bit [i] provides the interrupt status for CQ(i+1120) where i=0 to 31.[i]: Interrupt status for CQ(i+1120) |
|
0x10_0320 |
WC1 |
Completion Q interrupt status (bitwise) QP 1152-1183 (CQINTSTS37) |
This register provides the CQ interrupt status for QPs 1152 to 1183. Bit [i] provides the interrupt status for CQ(i+1152) where i=0 to 31.[i]: Interrupt status for CQ(i+1152) |
|
0x10_0324 |
WC1 |
Completion Q interrupt status (bitwise) QP 1184-1215 (CQINTSTS38) |
This register provides the CQ interrupt status for QPs 1184 to 1215. Bit [i] provides the interrupt status for CQ(i+1184) where i=0 to 31.[i]: Interrupt status for CQ(i+1184) |
|
0x10_0328 |
WC1 |
Completion Q interrupt status (bitwise) QP 1216-1247 (CQINTSTS39) |
This register provides the CQ interrupt status for QPs 1216 to 1247. Bit [i] provides the interrupt status for CQ(i+1216) where i=0 to 31.[i]: Interrupt status for CQ(i+1216) |
|
0x10_032C |
WC1 |
Completion Q interrupt status (bitwise) QP 1248-1279 (CQINTSTS40) |
This register provides the CQ interrupt status for QPs 1248 to 1279. Bit [i] provides the interrupt status for CQ(i+1248) where i=0 to 31.[i]: Interrupt status for CQ(i+1248) |
|
0x10_0330 |
WC1 |
Completion Q interrupt status (bitwise) QP 1280-1311 (CQINTSTS41) |
This register provides the CQ interrupt status for QPs 1280 to 1311. Bit [i] provides the interrupt status for CQ(i+1280) where i=0 to 31.[i]: Interrupt status for CQ(i+1280) |
|
0x10_0334 |
WC1 |
Completion Q interrupt status (bitwise) QP 1312-1343 (CQINTSTS42) |
This register provides the CQ interrupt status for QPs 1312 to 1343. Bit [i] provides the interrupt status for CQ(i+1312) where i=0 to 31.[i]: Interrupt status for CQ(i+1312) |
|
0x10_0338 |
WC1 |
Completion Q interrupt status (bitwise) QP 1344-1375 (CQINTSTS43) |
This register provides the CQ interrupt status for QPs 1344 to 1375. Bit [i] provides the interrupt status for CQ(i+1344) where i=0 to 31.[i]: Interrupt status for CQ(i+1344) |
|
0x10_033C |
WC1 |
Completion Q interrupt status (bitwise) QP 1376-1407 (CQINTSTS44) |
This register provides the CQ interrupt status for QPs 1376 to 1407. Bit [i] provides the interrupt status for CQ(i+1376) where i=0 to 31.[i]: Interrupt status for CQ(i+1376) |
|
0x10_0340 |
WC1 |
Completion Q interrupt status (bitwise) QP 1408-1439 (CQINTSTS45) |
This register provides the CQ interrupt status for QPs 1408 to 1439. Bit [i] provides the interrupt status for CQ(i+1408) where i=0 to 31.[i]: Interrupt status for CQ(i+1408) |
|
0x10_0344 |
WC1 |
Completion Q interrupt status (bitwise) QP 1440-1471 (CQINTSTS46) |
This register provides the CQ interrupt status for QPs 1440 to 1471. Bit [i] provides the interrupt status for CQ(i+1440) where i=0 to 31.[i]: Interrupt status for CQ(i+1440) |
|
0x10_0348 |
WC1 |
Completion Q interrupt status (bitwise) QP 1472-1503 (CQINTSTS47) |
This register provides the CQ interrupt status for QPs 1472 to 1503. Bit [i] provides the interrupt status for CQ(i+1472) where i=0 to 31.[i]: Interrupt status for CQ(i+1472) |
|
0x10_034C |
WC1 |
Completion Q interrupt status (bitwise) QP 1504-1535 (CQINTSTS48) |
This register provides the CQ interrupt status for QPs 1504 to 1535. Bit [i] provides the interrupt status for CQ(i+1504) where i=0 to 31.[i]: Interrupt status for CQ(i+1504) |
|
0x10_0350 |
WC1 |
Completion Q interrupt status (bitwise) QP 1536-1567 (CQINTSTS49) |
This register provides the CQ interrupt status for QPs 1536 to 1567. Bit [i] provides the interrupt status for CQ(i+1536) where i=0 to 31.[i]: Interrupt status for CQ(i+1536) |
|
0x10_0354 |
WC1 |
Completion Q interrupt status (bitwise) QP 1568-1599 (CQINTSTS50) |
This register provides the CQ interrupt status for QPs 1568 to 1599. Bit [i] provides the interrupt status for CQ(i+1568) where i=0 to 31.[i]: Interrupt status for CQ(i+1568) |
|
0x10_0358 |
WC1 |
Completion Q interrupt status (bitwise) QP 1600-1631 (CQINTSTS51) |
This register provides the CQ interrupt status for QPs 1600 to 1632. Bit [i] provides the interrupt status for CQ(i+1600) where i=0 to 31.[i]: Interrupt status for CQ(i+1600) |
|
0x10_035C |
WC1 |
Completion Q interrupt status (bitwise) QP 1632-1663 (CQINTSTS52) |
This register provides the CQ interrupt status for QPs 1632 to 1663. Bit [i] provides the interrupt status for CQ(i+1632) where i=0 to 31.[i]: Interrupt status for CQ(i+1632) |
|
0x10_0360 |
WC1 |
Completion Q interrupt status (bitwise) QP 1664-1695 (CQINTSTS53) |
This register provides the CQ interrupt status for QPs 1664 to 1695. Bit [i] provides the interrupt status for CQ(i+1664) where i=0 to 31.[i]: Interrupt status for CQ(i+1664) |
|
0x10_0364 |
WC1 |
Completion Q interrupt status (bitwise) QP 1696-1727 (CQINTSTS54) |
This register provides the CQ interrupt status for QPs 1696 to 1727. Bit [i] provides the interrupt status for CQ(i+1696) where i=0 to 31.[i]: Interrupt status for CQ(i+1696) |
|
0x10_0368 |
WC1 |
Completion Q interrupt status (bitwise) QP 1728-1759 (CQINTSTS55) |
This register provides the CQ interrupt status for QPs 1728 to 1759. Bit [i] provides the interrupt status for CQ(i+1728) where i=0 to 31.[i]: Interrupt status for CQ(i+1728) |
|
0x10_036C |
WC1 |
Completion Q interrupt status (bitwise) QP 1760-1791 (CQINTSTS56) |
This register provides the CQ interrupt status for QPs 1760 to 1791. Bit [i] provides the interrupt status for CQ(i+1760) where i=0 to 31.[i]: Interrupt status for CQ(i+1760) |
|
0x10_0370 |
WC1 |
Completion Q interrupt status (bitwise) QP 1792-1823 (CQINTSTS57) |
This register provides the CQ interrupt status for QPs 1792 to 1823. Bit [i] provides the interrupt status for CQ(i+1792) where i=0 to 31.[i]: Interrupt status for CQ(i+1792) |
|
0x10_0374 |
WC1 |
Completion Q interrupt status (bitwise) QP 1824-1855 (CQINTSTS58) |
This register provides the CQ interrupt status for QPs 1824 to 1855. Bit [i] provides the interrupt status for CQ(i+1824) where i=0 to 31.[i]: Interrupt status for CQ(i+1824) |
|
0x10_0378 |
WC1 |
Completion Q interrupt status (bitwise) QP 1856-1887 (CQINTSTS59) |
This register provides the CQ interrupt status for QPs 1856 to 1887. Bit [i] provides the interrupt status for CQ(i+1856) where i=0 to 31.[i]: Interrupt status for CQ(i+1856) |
|
0x10_037C |
WC1 |
Completion Q interrupt status (bitwise) QP 1888-1919 (CQINTSTS60) |
This register provides the CQ interrupt status for QPs 1888 to 1919. Bit [i] provides the interrupt status for CQ(i+1888) where i=0 to 31.[i]: Interrupt status for CQ(i+1888) |
|
0x10_0380 |
WC1 |
Completion Q interrupt status (bitwise) QP 1920-1951 (CQINTSTS61) |
This register provides the CQ interrupt status for QPs 1920 to 1951. Bit [i] provides the interrupt status for CQ(i+1920) where i=0 to 31.[i]: Interrupt status for CQ(i+1920) |
|
0x10_0384 |
WC1 |
Completion Q interrupt status (bitwise) QP 1952-1983 (CQINTSTS62) |
This register provides the CQ interrupt status for QPs 1952 to 1983. Bit [i] provides the interrupt status for CQ(i+1952) where i=0 to 31.[i]: Interrupt status for CQ(i+1952) |
|
0x10_0388 |
WC1 |
Completion Q interrupt status (bitwise) QP 1984-2015 (CQINTSTS63) |
This register provides the CQ interrupt status for QPs 1984 to 2016. Bit [i] provides the interrupt status for CQ(i+1984) where i=0 to 31.[i]: Interrupt status for CQ(i+1984) |
|
0x10_038C |
WC1 |
Completion Q interrupt status (bitwise) QP 2016-2047 (CQINTSTS64) |
This register provides the CQ interrupt status for QPs 2016 to 2047. Bit [i] provides the interrupt status for CQ(i+2016) where i=0 to 31.[i]: Interrupt status for CQ(i+2016) |
|
0x10_0390 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 0-31 (CNPSCHDSTS1REG) |
This register provides the CNP scheduled interrupt for QPs 0 to 31 |
|
0x10_0394 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 32-63 (CNPSCHDSTS2REG) |
This register provides the CNP scheduled interrupt for QPs 32 to 63 |
|
0x10_0398 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 64-95 (CNPSCHDSTS3REG) |
This register provides the CNP scheduled interrupt for QPs 64 to 95 |
|
0x10_039C |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 96-127 (CNPSCHDSTS4REG) |
This register provides the CNP scheduled interrupt for QPs 96 to 127 |
|
0x10_03A0 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 128-159 (CNPSCHDSTS5REG) |
This register provides the CNP scheduled interrupt for QPs 128 to 159 |
|
0x10_03A4 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 160-191 (CNPSCHDSTS6REG) |
This register provides the CNP scheduled interrupt for QPs 160 to 191 |
|
0x10_03A8 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 192-223 (CNPSCHDSTS7REG) |
This register provides the CNP scheduled interrupt for QPs 192 to 223 |
|
0x10_03AC |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 224-255 (CNPSCHDSTS8REG) |
This register provides the CNP scheduled interrupt for QPs 224 to 255 |
|
0x10_03B0 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 256-287 (CNPSCHDSTS9REG) |
This register provides the CNP scheduled interrupt for QPs 256 to 287 |
|
0x10_03B4 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 288-319 (CNPSCHDSTS10REG) |
This register provides the CNP scheduled interrupt for QPs 288 to 319 |
|
0x10_03B8 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 320-351 (CNPSCHDSTS11REG) |
This register provides the CNP scheduled interrupt for QPs 320 to 351 |
|
0x10_03BC |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 352-383 (CNPSCHDSTS12REG) |
This register provides the CNP scheduled interrupt for QPs 352 to 383 |
|
0x10_03C0 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 384-415 (CNPSCHDSTS13REG) |
This register provides the CNP scheduled interrupt for QPs 384 to 415 |
|
0x10_03C4 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 416-447 (CNPSCHDSTS14REG) |
This register provides the CNP scheduled interrupt for QPs 416 to 447 |
|
0x10_03C8 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 448-479 (CNPSCHDSTS15REG) |
This register provides the CNP scheduled interrupt for QPs 448 to 479 |
|
0x10_03CC |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 480-511 (CNPSCHDSTS16REG) |
This register provides the CNP scheduled interrupt for QPs 480 to 511 |
|
0x10_03D0 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 512-543 (CNPSCHDSTS17REG) |
This register provides the CNP scheduled interrupt for QPs 512 to 543 |
|
0x10_03D4 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 544-575 (CNPSCHDSTS18REG) |
This register provides the CNP scheduled interrupt for QPs 544 to 575 |
|
0x10_03D8 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 576-607 (CNPSCHDSTS19REG) |
This register provides the CNP scheduled interrupt for QPs 576 to 607 |
|
0x10_03DC |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 608-639 (CNPSCHDSTS20REG) |
This register provides the CNP scheduled interrupt for QPs 608 to 639 |
|
0x10_03E0 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 640-671 (CNPSCHDSTS21REG) |
This register provides the CNP scheduled interrupt for QPs 640 to 671 |
|
0x10_03E4 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 672-703 (CNPSCHDSTS22REG) |
This register provides the CNP scheduled interrupt for QPs 672 to 703 |
|
0x10_03E8 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 704-735 (CNPSCHDSTS23REG) |
This register provides the CNP scheduled interrupt for QPs 704 to 735 |
|
0x10_03EC |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 736-767 (CNPSCHDSTS24REG) |
This register provides the CNP scheduled interrupt for QPs 736 to 767 |
|
0x10_03F0 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 768-799 (CNPSCHDSTS25REG) |
This register provides the CNP scheduled interrupt for QPs 768 to 799 |
|
0x10_03F4 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 800-831 (CNPSCHDSTS26REG) |
This register provides the CNP scheduled interrupt for QPs 800 to 831 |
|
0x10_03F8 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 832-863 (CNPSCHDSTS27REG) |
This register provides the CNP scheduled interrupt for QPs 832 to 863 |
|
0x10_03FC |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 864-895 (CNPSCHDSTS28REG) |
This register provides the CNP scheduled interrupt for QPs 864 to 895 |
|
0x10_0400 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 896-927 (CNPSCHDSTS29REG) |
This register provides the CNP scheduled interrupt for QPs 896 to 927 |
|
0x10_0404 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 928-949 (CNPSCHDSTS30REG) |
This register provides the CNP scheduled interrupt for QPs 928 to 949 |
|
0x10_0408 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 960-991 (CNPSCHDSTS31REG) |
This register provides the CNP scheduled interrupt for QPs 960 to 991 |
|
0x10_040C |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 992-1023 (CNPSCHDSTS32REG) |
This register provides the CNP scheduled interrupt for QPs 992 to 1023 |
|
0x10_0410 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 1024-1055 (CNPSCHDSTS33REG) |
This register provides the CNP scheduled interrupt for QPs 1024 to 1055 |
|
0x10_0414 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 1056-1087 (CNPSCHDSTS34REG) |
This register provides the CNP scheduled interrupt for QPs 1056 to 1087 |
|
0x10_0418 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 1088-1119 (CNPSCHDSTS35REG) |
This register provides the CNP scheduled interrupt for QPs 1088 to 1119 |
|
0x10_041C |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 1120-1151 (CNPSCHDSTS36REG) |
This register provides the CNP scheduled interrupt for QPs 1120 to 1151 |
|
0x10_0420 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 1152-1183 (CNPSCHDSTS37REG) |
This register provides the CNP scheduled interrupt for QPs 1152 to 1183 |
|
0x10_0424 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 1184-1215 (CNPSCHDSTS38REG) |
This register provides the CNP scheduled interrupt for QPs 1184 to 1215 |
|
0x10_0428 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 1216-1247 (CNPSCHDSTS39REG) |
This register provides the CNP scheduled interrupt for QPs 1216 to 1247 |
|
0x10_042C |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 1248-1279 (CNPSCHDSTS40REG) |
This register provides the CNP scheduled interrupt for QPs 1248 to 1279 |
|
0x10_0430 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 1280-1311 (CNPSCHDSTS41REG) |
This register provides the CNP scheduled interrupt for QPs 1280 to 1311 |
|
0x10_0434 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 1312-1343 (CNPSCHDSTS42REG) |
This register provides the CNP scheduled interrupt for QPs 1312 to 1343 |
|
0x10_0438 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 1344-1375 (CNPSCHDSTS43REG) |
This register provides the CNP scheduled interrupt for QPs 1344 to 1375 |
|
0x10_043C |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 1376-1407 (CNPSCHDSTS44REG) |
This register provides the CNP scheduled interrupt for QPs 1376 to 1407 |
|
0x10_0440 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 1408-1439 (CNPSCHDSTS45REG) |
This register provides the CNP scheduled interrupt for QPs 1408 to 1439 |
|
0x10_0444 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 1440-1471 (CNPSCHDSTS46REG) |
This register provides the CNP scheduled interrupt for QPs 1440 to 1471 |
|
0x10_0448 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 1472-1503 (CNPSCHDSTS47REG) |
This register provides the CNP scheduled interrupt for QPs 1472 to 1503 |
|
0x10_044C |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 1504-1535 (CNPSCHDSTS48REG) |
This register provides the CNP scheduled interrupt for QPs 1504 to 1535 |
|
0x10_0450 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 1536-1567 (CNPSCHDSTS49REG) |
This register provides the CNP scheduled interrupt for QPs 1536 to 1567 |
|
0x10_0454 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 1568-1599 (CNPSCHDSTS50REG) |
This register provides the CNP scheduled interrupt for QPs 1568 to 1599 |
|
0x10_0458 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 1600-1631 (CNPSCHDSTS51REG) |
This register provides the CNP scheduled interrupt for QPs 1600 to 1631 |
|
0x10_045C |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 1632-1663 (CNPSCHDSTS52REG) |
This register provides the CNP scheduled interrupt for QPs 1632 to 1663 |
|
0x10_0460 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 1664-1695 (CNPSCHDSTS53REG) |
This register provides the CNP scheduled interrupt for QPs 1664 to 1695 |
|
0x10_0464 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 1696-1727 (CNPSCHDSTS54REG) |
This register provides the CNP scheduled interrupt for QPs 1696 to 1727 |
|
0x10_0468 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 1728-1759 (CNPSCHDSTS55REG) |
This register provides the CNP scheduled interrupt for QPs 1728 to 1759 |
|
0x10_046C |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 1760-1791 (CNPSCHDSTS56REG) |
This register provides the CNP scheduled interrupt for QPs 1760 to 1791 |
|
0x10_0470 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 1792-1823 (CNPSCHDSTS57REG) |
This register provides the CNP scheduled interrupt for QPs 1792 to 1823 |
|
0x10_0474 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 1824-1855 (CNPSCHDSTS58REG) |
This register provides the CNP scheduled interrupt for QPs 1824 to 1855 |
|
0x10_0478 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 1856-1887 (CNPSCHDSTS59REG) |
This register provides the CNP scheduled interrupt for QPs 1856 to 1887 |
|
0x10_047C |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 1888-1919 (CNPSCHDSTS60REG) |
This register provides the CNP scheduled interrupt for QPs 1888 to 1919 |
|
0x10_0480 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 1920-1951 (CNPSCHDSTS61REG) |
This register provides the CNP scheduled interrupt for QPs 1920 to 1951 |
|
0x10_0484 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 1952-1983 (CNPSCHDSTS62REG) |
This register provides the CNP scheduled interrupt for QPs 1952 to 1983 |
|
0x10_0488 |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 1984-2015 (CNPSCHDSTS63REG) |
This register provides the CNP scheduled interrupt for QPs 1984 to 2015 |
|
0x10_048C |
RO |
CNP Packed scheduled interrupt status (bitwise) QP 2016-2047 (CNPSCHDSTS64REG) |
This register provides the CNP scheduled interrupt for QPs 2016 to 2047 |
|
Per QP Registers |
|||
|
0x18_0000 + ((i-1) x 0x0100) |
RW |
QP Configuration QPi (QPCONFi) |
This register defines the basic configuration of QP. This register is generated based on the parameter C_NUM_QP (where i = 1 to C_NUM_QP). Register offset for per-QP is 0x18_0000, 0x18_0004 and so on for the subsequent offsets. • [0]: QP enable – Should be set to 1 for all active QPs. A disabled QP will not be able to receive or transmit packets. • [2]: RQ interrupt enable – When enabled, allows the receive queue interrupt to be generated for every new packet received on the receive queue • [3]: CQ interrupt enable – When enabled, allows the completion queue interrupt to be generated for every send work queue entry completion • [4]: HW Handshake disable – This bit when reset to 0 enables the HW handshake ports for doorbell exchange. If set, all doorbell values are exchanged through writes through the AXI4 or AXI4-Lite interface. • [5]: CQE write enable – This bit when set, enables completion queue entry writes. The writes are disabled when this bit is reset. CQE writes can be enabled to debug failed completions. • [6]: QP under recovery. This bit need to be set in the fatal clearing process. • [7]: QP configured for IPv4 or IPv6 ° 0 - IPv4 ° 1 - IPv6 • [10:8]: Path MTU ° 000 – 256B (default) ° 001 – 512B ° 010 – 1024B ° 011 – 2048B ° 100 - 4096B ° 101 to 111 - Reserved • [31:16]: RQ Buffer size (in multiple of 256B). This is the size of each buffer element in the request and not the size of the entire request. The programmed value should be the power of 2 for expected behavior. |
|
0x18_0004 + ((i-1) x 0x0100) |
RW |
QP advanced configuration QPi (QPADVCONFi) |
This register is generated based on the parameter C_NUM_QP (where i = 2 to C_NUM_QP). This register is not present for QP1. • [5:0]: Traffic class (keep default reset value) • [15:8]: Time to live • [31:16]: Partition Key |
|
0x18_0008 + ((i-1) x 0x0100) |
RW |
RCV Q Buffer base address QPi (RQBAi) |
This register is generated based on the parameter C_NUM_QP (where i = 1 to C_NUM_QP). This register provides the base address of the RDMA Receive queue buffer. [31:8]: Receive Q Buffer Base address addr (256 B aligned). 256 B is the total (individual rq buffer element size)* rq_depth |
|
0x18_00C0 + (i-1) x 0x0100) |
RW |
RCV Q Buffer base address QPi (RQBAMSBi) |
This register is generated based on the parameter C_NUM_QP (where i = 1 to C_NUM_QP). This register provides the msb base address of the RDMA Receive queue buffer. [63:32]: Receive Q Buffer Base address addr (256 B aligned). 256 B is the total (individual rq buffer element size)* rq_depth |
|
0x18_0010 + ((i-1) x 0x0100) |
RW |
SEND Q base address QPi (SQBAi) |
This register is generated based on the parameter C_NUM_QP (where i = 1 to C_NUM_QP). This register provides the base address of the RDMA Send queue buffer. [31:5]: Send Q base address (32 B aligned) |
|
0x18_00C8 + ((i-1) x 0x0100) |
|
SEND Q base address msb QPi (SQBAMSBi) |
This register is generated based on the parameter C_NUM_QP (where i = 1 to C_NUM_QP). This register provides the msb base address of the RDMA Send queue buffer. [63:32]: Send Q base address (32 B aligned) |
|
0x18_0018 + ((i-1) x 0x0100) |
RW |
CQ base address QPi (CQBAi) |
This register is generated based on the parameter C_NUM_QP (where i = 1 to C_NUM_QP). This register provides the base address of the RDMA Completion queue buffer. [31:5]: Send CQ base address (32 B aligned) |
|
0x18_00D0 + ((i-1) x 0x0100) |
RW |
CQ base address msb QPi (CQBAMSBi) |
This register is generated based on the parameter C_NUM_QP (where i = 1 to C_NUM_QP). This register provides the msb base address of the RDMA Completion queue buffer. [63:32]: Send CQ base address (32 B aligned) |
|
0x18_0020 + ((i-1) x 0x0100) |
RW |
RCV Q Write pointer DB address QPi (RQWPTRDBADDi) |
This register is generated based on the parameter C_NUM_QP (where i = 1 to C_NUM_QP). This register provides the address of the Receive Queue doorbell register. Upon reception of a new incoming RDMA SEND packet, the ERNIC IP updates the RQ doorbell values in the address pointed to by this register. [31:0]: RCV Q write pointer Doorbell address |
|
0x18_0024 + ((i-1) x 0x0100) |
RW |
RCV Q Write pointer DB address msb QPi (RQWPTRDBADDMSBi) |
This register is generated based on the parameter C_NUM_QP (where i = 1 to C_NUM_QP). This register provides the msb address of the Receive Queue doorbell register. Upon reception of a new incoming RDMA SEND packet, the ERNIC IP updates the RQ doorbell values in the address pointed to by this register. [63:32]: RCV Q write pointer Doorbell address msb |
|
0x18_0028 + ((i-1) x 0x0100) |
RW |
CQ DB address QPi (CQDBADDi) |
This register is generated based on the parameter C_NUM_QP (where i = 1 to C_NUM_QP). this register provides the address of the Completion Queue doorbell register. Upon completion of a new SEND Work queue entry, the ERNIC IP updates the CQ doorbell values in the address pointed to by this register. [31:0]: Send CQ Doorbell address |
|
0x18_002C + ((i-1) x 0x0100) |
RW |
CQ DB address QPi (CQDBADDMSBi) |
This register is generated based on the parameter C_NUM_QP (where i = 1 to C_NUM_QP). this register provides the msb address of the Completion Queue doorbell register. Upon completion of a new SEND Work queue entry, the ERNIC IP updates the CQ doorbell values in the address pointed to by this register. [63:32]: Send CQ Doorbell address |
|
0x18_0030 + ((i-1) x 0x0100) |
RO |
CQ head pointer QPi (CQHEADi) |
This register is generated based on the parameter C_NUM_QP (where i = 1 to C_NUM_QP). This status register gives the Send completion Queue doorbell value and provides information about the Send WQEs that have been completed. This is the doorbell value that is written by the ERNIC IP to the address pointed to by the CQDBADDi register. • [15:0]: CQ head pointer • [31:0]: Reserved |
|
0x18_0034 + ((i-1) x 0x0100) |
RW |
RQ Consumer Index QPi (RQCIi) |
This register is generated based on the parameter C_NUM_QP (where i = 1 to C_NUM_QP). This register is updated by the target application on consuming a new receive queue entry. Once consumed, the RQ entry can be over written by the ERNIC IP. The RQCI index can also be updated through the side band interface. • [15:0]: RCV Q Consumer Index Doorbell • [31:16]: Reserved |
|
0x18_0038 + ((i-1) x 0x0100) |
RW |
SQ Producer index QPi (SQPIi) |
This register is generated based on the parameter C_NUM_QP (where i = 1 to C_NUM_QP). This register is updated by the target application when it posts a new Send Work Queue entry. The SQPI can also be updated through the side band interface. The Send Queue is a circular buffer. The CQHEAD register for the corresponding QP provides information about the Work Queue entries that have been completed and can be over written by the target application. • [15:0]: Send Q Producer Index Doorbell • [31:16]: Reserved |
|
0x18_003C + ((i-1) x 0x0100) |
RW |
Q Depth QPi (QDEPTHi) |
This register is generated based on the parameter C_NUM_QP (where i = 1 to C_NUM_QP). This register defines the queue depths for send, completion and receive queues. • [15:0]: Send Q depth (Send CQ will of the same depth) • [31:16]: Receive Q depth |
|
0x18_0040 + ((i-1) x 0x0100) |
RW |
SEND Q PSN for QPi (SQPSNi) |
This register is initialized at connection time by the SW. After that the HW updates it for every outgoing packet and should not be updated by the SW. This register is generated based on the parameter C_NUM_QP (where i = 2 to C_NUM_QP). This register does not exist for QP1. [23:0]: Send Q PSN |
|
0x18_0044 + ((i-1) x 0x0100) |
RW |
Last RQ req for QPi (LSTRQREQi) |
This register provides the last incoming RQ packet details. This register is generated based on the parameter C_NUM_QP (where i = 2 to C_NUM_QP). This register does not exist for QP1. • [23:0]: RCV Q PSN • [31:24]: RCV Q opcode |
|
0x18_0048 + ((i-1) x 0x0100) |
RW |
Destination QP configuration for QPi (DESTQPCONFi) |
This register is generated based on the parameter C_NUM_QP (where i = 1 to C_NUM_QP). This register is configured at connection time by the SW and provides the remote QPID connected to this QP. All outgoing packets from this QP are sent with this QPID as the destination QPID. [23:0]: Destination Connected QPID |
|
0x18_0050 + ((i-1) x 0x0100) |
RW |
MAC destination address LSB QPi (MACDESADDLSBi) |
This register is generated based on the parameter C_NUM_QP (where i = 1 to C_NUM_QP). This register is configured at connection time by the SW and provides the MAC address of the remote host connected to this QP. All outgoing packets from this QP are sent with this MAC address (LSB) as the destination MAC address. [31:0]: MAC destination address LSB |
|
0x18_0054 + ((i-1) x 0x0100) |
RW |
MAC destination address MSB QPi (MACDESADDMSBi) |
This register is generated based on the parameter C_NUM_QP (where i = 1 to C_NUM_QP). This register is configured at connection time by the SW and provides the MAC address of the remote host connected to this QP. All outgoing packets from this QP are sent with this MAC address (MSB) as the destination MAC address. [15:0]: MAC destination address MSB |
|
0x18_0060 + ((i-1) x 0x0100) |
RW |
IP destination address 1 QPi (IPDESADDR1i) |
This register is generated based on the parameter C_NUM_QP (where i = 1 to C_NUM_QP). If the remote host for this QP is configured using the IPv4 protocol, then this register indicates an IPv4 address. If the remote host is configured using the IPv6 protocol, this register then indicates the IPv6 destination address. [31:0]: IP Destination address LSB1 |
|
0x18_0064 + ((i-1) x 0x0100) |
RW |
IP destination address 2 QPi (IPDESADDR2i) |
This register is generated based on the parameter C_NUM_QP (where i = 1 to C_NUM_QP). If the remote host is configured using the IPv6 protocol, this register indicates an IPv6 destination address [63:32]. If the remote host of this QP is configured using the IPv4 protocol, then this register is not used. [31:0]: IP Destination address LSB2 |
|
0x18_0068 + ((i-1) x 0x0100) |
RW |
IP destination address 3 QPi (IPDESADDR3i) |
This register is generated based on the parameter C_NUM_QP (where i = 1 to C_NUM_QP). If the remote host is configured using the IPv6 protocol, this register indicates an IPv6 destination address [95:64]. IF the remote host of this QP is configured using the IPv4 protocol, then this register is not used. [31:0]: IP Destination address MSB1 |
|
0x18_006C + ((i-1) x 0x0100) |
RW |
IP destination address 4 QPi (IPDESADDR4i) |
This register is generated based on the parameter C_NUM_QP (where i = 1 to C_NUM_QP). If the remote host is configured using the IPv6 protocol, this register indicates an IPv6 destination address [127:96]. If the remote host of this QP is configured using the IPv4 protocol, then this register is not used. [31:0]: IP Destination address MSB2 |
|
0x18_004C + ((i-1) x 0x0100) |
RW |
Timeout Configuration Register for QPi (TIMEOUTCONFi) |
This register is generated based on the parameter C_NUM_QP (where i = 1 to C_NUM_QP). It provides the timeout configuration QPi. This register does not exist for QP1. • [5:0]: Timeout value • [7:6]: Reserved • [10:8]: Maximum retry count • [13:11]: Maximum RNR retry count • [15:14]: Reserved • [20:16]: RNR NACK Timeout value for outgoing packets • [31:21]: Reserved |
|
0x18_0080 + ((i-1) x 0x0100) |
RO |
Status Sender sequence number QPi (STATSSNi) |
This register is generated based on the parameter C_NUM_QP (where i = 2 to C_NUM_QP). This register does not exist for QP1. [23:0]: Current outgoing SSN (same as outgoing MSN) |
|
0x18_0084 + ((i-1) x 0x0100) |
RO |
Status Message sequence number QPi (STATMSN) |
This register is generated based on the parameter C_NUM_QP (where i = 2 to C_NUM_QP). This register does not exist for QP1. [23:0]: Current expected incoming MSN |
|
0x18_0088 + ((i-1) x 0x0100) |
RO |
Status QPi (STATQPi) |
This register provides the QP status for every QP. This register is generated based on the parameter C_NUM_QP (where i = 1 to C_NUM_QP). • [0]: QP in fatal status • [1]: RCV Q ovfl (outgoing RNR NACK) • [2]: Send Q full • [3]: Outstanding Q full • [4]: CQ FIFO full • [8:5]: Reserved • [9]: Send Q empty. This bit signifies that there are no SQEs left to process. However, it does not imply that all the SEND WQEs were acknowledged by the remote host. • [10]: Outstanding Q empty • [11]: QP packet was retried • [15:12]: Reserved • [22:16]: NACK syndrome received (Read/Write) • [23]: Reserved • [26:24]: Current retry count (Read/Write) • [27]: Reserved • [30:28]: Current RNR nack count for inc resp packets (Read/Write) • [31]: Reserved |
|
0x18_008C + ((i-1) x 0x0100) |
RO |
Status Current SQ ptr under process (STATCURSQPTRi) |
This register is generated based on the parameter C_NUM_QP (where i = 2 to C_NUM_QP). [15:0]: Current SQ pointer that is under process. This shows the number of WQEs that are outstanding and awaiting a response from the remote host. |
|
0x18_0090 + ((i-1) x 0x0100) |
RO |
Status Response PSN for QPi (STATRESPSNi) |
This register is generated based on the parameter C_NUM_QP (where i = 2 to C_NUM_QP). This register does not exist for QP1. [23:0]: Expected response PSN |
|
0x18_0094 + ((i-1) x 0x0100) |
RO |
Status RQ buffer current address for QPi (STATRQBUFCAi) |
This register is generated based on the parameter C_NUM_QP (where i = 2 to C_NUM_QP). [31:8]: Receive Q Buffer current addr (256 B aligned) |
|
0x18_00D8 + ((i-1) x 0x0100) |
RO |
Status RQ buffer current msb address for QPi (STATRQBUFCAMSBi) |
This register is generated based on the parameter C_NUM_QP (where i = 2 to C_NUM_QP). [63:32]: Receive Q Buffer current addr msb (256 B aligned) |
|
0x18_0098 + ((i-1) x 0x0100) |
RO |
Status of WQEs posted to QPi (STATWQEi) |
This register is generated based on the parameter C_NUM_QP (where i = 2 to C_NUM_QP). [15:0]: Count of WQEs pushed by QP MGR for this QP |
|
0x18_009C + ((i-1) x 0x0100) |
RO |
Status RQ Producer index DB QPi (STATRQPIDBi) |
This register is generated based on the parameter C_NUM_QP (where i = 2 to C_NUM_QP). [15:0]: RCV Q Producer Index DB |
|
0x18_00B0 + ((i-1) x 0x0100) |
RW |
Protection domain number |
This register is generated based on the parameter C_NUM_QP (where i = 2 to C_NUM_QP). This register is 24-bit and contains the PD number assigned to the QP. Note: Only one memory region can be associated per QP. |