Port Descriptions - Port Descriptions - 4.0 English - PG332

Clocking and Reset

m_axi_aclk

I

1

AXI4

AXI4 clock

m_axi_aresetn

I

1

AXI4 reset (active-Low)

s_axi_lite_aclk

I

1

AXI4

AXI4-Lite clock

s_axi_lite_aresetn

I

1

AXI4-Lite reset (active-Low)

system_resetn

O

1

System reset

cmac_rx_clk

I

1

RX user clock output from CMAC

cmac_rx_rst

I

1

RX reset for user logic from CMAC

cmac_tx_clk

I

1

TX user clock output from CMAC

cmac_tx_rst

I

1

TX reset for user logic from CMAC

Response Handler AXI4 Master Interface

resp_hndler_m_axi_*

I/O

AXI4

This interface is used by the response handler to write completions in the completion queue present in the DDR. See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) [Ref 8] for more information on the AXI4 signal.

RX Packet Handler AXI4 Master Interface to DDR

rx_pkt_hndler_ddr_m_axi*

I/O

AXI4

This interface is used by the RX packet handler module to push the data from incoming MAD, SEND, and RDMA WRITE packets to RQ buffer in the DDR. Supports only 64B aligned transaction. See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) [Ref 8] for more information on the AXI4 signal.

RX Packet Handler AXI4 Master Read Response Interface

rx_pkt_hndler_rdrsp_m_axi*

I/O

AXI4

This interface is used by the RX packet handler to write the data received in read responses to the DDR. See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) [Ref 8] for more information on the AXI4 signal.

AXI4-Stream Slave Interface for Incoming RoCE Traffic

roce_cmac_s_ axis_*

I/O

AXI4-
Stream

This interface provides RoCE packets from the network interface to the IP. See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) [Ref 8] for more information on the AXI4 signal.

AXI4-Stream Slave Interface for Incoming Non-RoCE Traffic

non_roce_cmac_s_ axis_*

I/O

AXI4-
Stream

This interface provides non-RoCE packets from the network interface to the IP. See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) [Ref 8] for more information on the AXI4 signal.

Non-RoCE AXI4-Stream Interface from DMA Module

non_roce_dma_s_axis_*

I/O

AXI4-
Stream

Incoming non-RDMA path from DMA module to IP. See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) [Ref 8] for more information on the AXI4 signal.

Non-RoCE AXI4-Stream Interface to DMA Module

non_roce_dma_m_axis_*

I/O

AXI4-
Stream

AXI4 Outgoing non-RDMA path from IP to DMA module. See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) [Ref 8] for more information on the AXI4 signal.

CMAC AXI4-Stream Interface

cmac_m_axis_*

I/O

cmac_tx_clk

This interface is used to send out RoCE and non-RoCE packets from ERNIC to CMAC.

WQE Processor AXI Master Interface

wqe_proc_top_m_axi_*

I/O

AXI4

This interface is used by the WQE processor engine to read the data sent in outgoing RDMA SEND/WRITE and READ responses from the local buffer. See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) [Ref 8] for more information on the AXI4 signal.

WQE Processor AXI4 Master Interface to DDR

wqe_proc_wr_ddr_m_axi_*

I/O

AXI4

This interface is used by the WQE processor to write the data of outgoing write packets in the write retry buffer. See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) [Ref 8] for more information on the AXI4 signal.

AXI4-Lite Slave Interface for Register Programming

s_axi_lite_*

I/O

AXI4-
Lite

This interface is used by the processor to configure the ERNIC registers. See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) [Ref 8] for more information on the AXI4 signal.

QP Manager AXI4 Master Interface

qp_mgr_m_axi_*

I/O

AXI4

This interface is used by the QP manager to fetch the send queue WQEs from the DDR. See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) [Ref 8] for more information on the AXI4 signal.

Invalidate or Immediate Data AXI4-Stream Interface

ieth_immdt_m_axis_*

I/O

AXI4S

This interface is used to provide IETH or Immdt headers along with 32-bit additional data to external hardware logic. The use of this information is left to user application.

HW Handshake Ports for RQ Doorbells

rx_pkt_hndler_o_rq_db_data

O

32

AXI4

RDMA-SEND Producer Index Doorbell Value from ERNIC

rx_pkt_hndler_o_rq_db_addr

O

13

AXI4

RDMA-SEND Producer Index Doorbell Address (4 Bytes per QP; for 127 QPs)

rx_pkt_hndler_o_rq_db_data_valid

O

1

AXI4

RDMA-SEND Producer Index Doorbell Valid. When this signal is asserted High, rx_pkt_hndler_o_rq_db_addr and rx_pkt_hndler_o_rq_db_data are valid.

Until rx_pkt_hndler_i_rq_db_rdy is not sampled High, this signal remains asserted and, rx_pkt_hndler_o_rq_db_addr and rx_pkt_hndler_o_rq_db_data signals will hold the same values.

rx_pkt_hndler_i_rq_db_rdy

I

1

AXI4

Ready from the target signaling data and address are accepted

HW Handshake Ports for CQ Doorbells

resp_hndler_o_send_cq_db_cnt

O

32

AXI4

Send WQE Completion queue Doorbell count from ERNIC

resp_hndler_o_send_cq_db_addr

O

13

AXI4

Send WQE Completion queue Doorbell address (4 Bytes per QP; for 127 QPs)

resp_hndler_o_send_cq_db_cnt_valid

O

1

AXI4

Send WQE Completion Doorbell Valid. When this signal is asserted High, resp_hndler_o_send_cq_db_addr and resp_hndler_o_send_cq_db_cnt are valid. Until resp_hndler_i_send_cq_db_rdy is not sampled High, this signal remains asserted and, resp_hndler_o_send_cq_db_addr and resp_hndler_o_send_cq_db_cnt signals will hold the same values.

resp_hndler_i_send_cq_db_rdy

I

1

AXI4

Send WQE Completion Doorbell Ready. Ready signal should go High when the target application accepts the current doorbell transaction.

HW Handshake Ports for SQ PI Doorbells

i_qp_sq_pidb_hndshk

I

16

AXI4

Send WQE Producer Index Doorbell Value from target application

i_qp_sq_pidb_wr_addr_hndshk

I

32

AXI4

Send WQE Producer Index Doorbell Address

i_qp_sq_pidb_wr_valid_hndshk

I

1

AXI4

Send WQE Producer Index Doorbell Valid. After the target application posts WQE(s), it should assert this signal High with valid i_qp_sq_pidb_wr_addr_hndshk and i_qp_sq_pidb_hndshk. Target application should keep this signal asserted and hold i_qp_sq_pidb_wr_addr_hndshk and i_qp_sq_pidb_hndshk signals until it samples o_qp_sq_pidb_wr_rdy as High.

o_qp_sq_pidb_wr_rdy

O

1

AXI4

Send WQE Producer Index Doorbell Ready. Ready signal asserted High when ERNIC accepts the Doorbell value.

HW Handshake Ports for RQ CI Doorbells

i_qp_rq_cidb_hndshk

I

16

AXI4

RDMA-SEND Consumer Index Doorbell value from target application

i_qp_rq_cidb_wr_addr_hndshk

I

32

AXI4

RDMA-SEND Consumer Index Doorbell register address

i_qp_rq_cidb_wr_valid_hndshk

I

1

AXI4

RDMA-SEND Consumer Index Doorbell Valid. After target application processes incoming RDMA-SEND command(s), it should assert this signal High with valid i_qp_rq_cidb_wr_addr_hndshk and i_qp_rq_cidb_hndshk. Target application should keep this signal asserted and hold i_qp_rq_cidb_wr_addr_hndshk and i_qp_rq_cidb_hndshk signals until it samples o_qp_rq_cidb_wr_rdy as High.

o_qp_rq_cidb_wr_rdy

O

1

AXI4

RDMA SEND Consumer Index Doorbell value is accepted by ERNIC

Priority Flow Control Ports

stat_rx_pause_req[8:0]

I

9

cmac_rx_clk

Pause request signal. This signal gets asserted by CMAC IP for valid quanta period.

ctl_tx_pause_req[8:0]

O

9

cmac_tx_clk

This bus gets asserted when buffer thresholds are between XON and XOFF. priority bit is set through priority register.

ctl_tx_resend_pause

O

1

cmac_tx_clk

This signal is hardwired to 0 and can be connected to CMAC IP signal.

Interrupts

rnic_intr

O

1

AXI4

This bit is set when any one of the interrupts in the register INTEN occurs.

Debug Counter Enabling Signals

o_global_dbg_cnt_en

O

1

AXI4

Enables debug signals

o_global_dbg_cnt_clr

O

1

AXI4

Clears the debug counters