Navigating Content by Design Process - Navigating Content by Design Process - 4.0 English - PG332

Xilinx Embedded RDMA Enabled NIC LogiCORE IP Product Guide (PG332)

Document ID
PG332
Release Date
2022-12-02
Version
4.0 English

Xilinx ® documentation is organized around a set of standard design processes to help you find relevant content for your current development task. This document covers the following design processes:

Hardware, IP, and Platform Development: Creating the PL IP blocks for the hardware platform, creating PL kernels, subsystem functional simulation, and evaluating the Vivado ® timing, resource and power closure. Also involves developing the hardware platform for system integration. Topics in this document that apply to this design process include:

° Port Descriptions

° Register Space

° Clocking

° Resets

° Customizing and Generating the Core

° Example Design