ERNIC IP provides a single interrupt line, which is generated on different interrupts status signals defined in INTEN register. Each of these interrupt lines can be enabled by writing a 1 to the corresponding bits of the Interrupt Enable INTEN register. On receiving an ORed interrupt the SW can read the INTSTS register to know the cause of the interrupt.
Interrupt bits 4 and 6 inform the drivers about a WQE completion or an incoming RDMA SEND respectively. These interrupts can be enabled or disabled on a per QP basis. Bit [2] of the QPCONFi registers allows selective enabling of Receive Queue interrupts per QP. Similarly, bit [3] of the QPCONFi registers allows selective enabling of Send Completion Queue interrupts. In general QPs that require SW handling should have this option enabled. The QPs that are directly handled by the hardware will be informed through the hardware handshake ports and corresponding interrupt enable bits can be disabled. Such QPs should have the hardware handshake disable QPCONFi[4] bit reset to 0.
The RQINTSTSn and CQINTSTSn registers provide bitwise information about the QPs that have a pending RQ or CQ entry to be serviced.
These registers should be read by the SW on receiving an RQ or CQ interrupt respectively to know the QPs that are required to be serviced. These interrupt status should be cleared upon successful handling by writing a 1 to the respective bits.