General Design Guidelines - General Design Guidelines - 4.0 English

A typical ERNIC subsystem would include one or more MAC hard/soft IPs. An AXI interconnect would also be required to connect the various AXI interfaces exposed by the ERNIC IP. A DRAM can be a part of the solution which would require a DRAM controller to be instantiated as well.

Figure 3-1: ERNIC Interfaces
X-Ref Target - Figure 3-1

This Figure shows the various ERNIC IP interfaces. The interfaces shown as interfacing with DDR may interface with any memory mapped region. Refer to Table: ERNIC IP Ports for details on each of these interfaces. The AXI4 and the AXI4-Stream interfaces are 512 bits wide and are mainly used for data transfers. The ERNIC IP provides sideband interfaces to allow for efficient exchange of queue pair related doorbells. These side band interfaces can be enabled or disabled for each queue pair (QP) based on the configuration.

The ERNIC IP has one AXI4-Lite slave interface to access the register space. The details of the memory map required for this slave interface is shown in the following table.

Table 3-1: Address Space Allocation Requirement for Slave Interfaces
Slave Interface	Size	Unit	Description
ERNIC AXI4-Lite slave interface	2	MB	ERNIC register interface

Apart from these, the IP also requires some memory regions to be allocated for some specific data structures. These memory regions may be mapped to a local DRAM or an AXI BRAM or any other memory mapped slave. Ensure that there is adequate bandwidth on these memory interfaces based on the line rate that ERNIC should achieve.

Table 3-2: ERNIC IP Memory Requirement
Memory Region	Size	Unit	Description
Error buffer	64	KB	256 packets of 256 bytes each. Packets that fail packet validation are sent to the error buffer along with 4 bytes of error syndrome
Send Queue	16	MB	2048 QPs of depth 128 locations and each SQE is of 64 bytes each
Receive Queue	256	MB	2048 QPs of depth 128 locations and each RQE is of 1024 bytes each
Send completion Queue	1	MB	2048 QPs of depth 128 locations and each CQE is of 4 bytes each
Write Retry buffers	16	MB	Buffers of 4K size each for 256 QPs and each QP with up to 16 outstanding transactions
Notes: 1. Use the Vivado implementation strategy — Performance_RefinePlacement — when using the ERNIC with more than 256 QPs.

General Design Guidelines - General Design Guidelines - 4.0 English - PG332

Xilinx Embedded RDMA Enabled NIC LogiCORE IP Product Guide (PG332)