• Support for RDMA functionality
° RoCE v2
° Packet retransmission on errors are handled in the hardware by the IP.
• 100 Gb/s line rate
• Support for Reliable Connection (RC) RDMA transport service types
• QP1 support for sending and receiving MAD packets
• Hardware handshake mode on user interface to support hardware RDMA applications in the user logic
• Supports incoming and outgoing RDMA SEND, RDMA READ, RDMA WRITE, RDMA SEND WITH IMM, RDMA WRITE WITH IMM, and RDMA SEND WITH INVALIDATE message types.
• Designed to scale up to 2047 RDMA Queue pairs (3)
• Support for IPv4 and IPv6 packets
• Support for Explicit Congestion Notification (ECN)
• Supports Priority flow control with different priorities for RoCE and non-RoCE traffic.
• Supports memory registrations and protection domains
|
LogiCORE™ IP Facts Table |
|
|---|---|
|
Core Specifics |
|
|
Supported Device Family (1) |
Versal® ACAP Kintex UltraScale+ ™ , Virtex® UltraScale ™ , Virtex UltraScale+, Zynq® UltraScale+ |
|
Supported User Interfaces |
AXI4-Lite, AXI4, and AXI4-Stream |
|
Resources |
|
|
Provided with Core |
|
|
Design Files |
Encrypted RTL |
|
Example Design |
Verilog |
|
Test Bench |
Not Provided |
|
Constraints File |
Xilinx Design Constraints (XDC) |
|
Simulation Model |
Not Provided |
|
Supported
|
Linux kernel drivers and user space libraries for RDMA |
|
Tested Design Flows (2) |
|
|
Design Entry |
Vivado® Design Suite Vivado IP integrator |
|
Simulation |
For supported simulators, see the
|
|
Synthesis |
Vivado Synthesis |
|
Support |
|
|
Release Notes and Known Issues |
N/A |
|
All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775 |
|
Notes: 1. For a complete list of supported devices, see the Vivado IP catalog.
2.
For the supported versions of third-party tools, see the
3. For -1 speed grade devices design might have timing violations for more than 64 QP configuration. |
|