The ERNIC IP interfaces with any Ethernet MAC IP using an AXI4-Stream interface. Access to DDR or any other memory region is necessary for reading and writing various data structures for RDMA packet processing. This connection is achieved using multiple AXI4 interfaces. The IP works on a 512-bit internal datapath that can be completely hardware accelerated without any software intervention for data transfer. All recoverable faults like retransmission due to packet drops are also handled entirely in the hardware.
The ERNIC IP implements embedded RNIC functionality. As a result, only the following subset of RoCE v2 functionality is implemented compared to a general purpose RNIC:
• Support for RDMA SEND, RDMA READ, RDMA WRITE, RDMA SEND INVALIDATE, RDMA SEND IMMEDIATE, and RDMA WRITE IMMEDIATE for incoming and outgoing packets. Atomic operations are not supported.
• Support for up to 2046 connections.
• Scalable design of up to 2047 RDMA Queue pairs.
Note: Default Vivado strategies allow for the timing to pass up to 127 queue pairs. To match the timing for 2047 queue pairs, use the Vivado strategy — Performance_refinePlacement.
• Supports dynamic memory registration.
• Hardware handshake mechanism for efficient doorbell exchange with the user application logic.
Note: When switching in the handshake mode, the software layer should not have any traffic on that particular QP.