This chapter contains information about the ERNIC core example design. The example design consists of the following modules:
• Clock and Reset Generator (simulation only)
• Register Configuration Module
• Send, Read Response, and ACK Generator
• WQE generator
• TX Path Checker
• RX Path Checker
This Figure shows the top-level example design architecture.
Apart from the ERNIC IP, the example design integrates the following modules:
• Register Configuration Module : This module configures all the required registers of the ERNIC IP.
• Packet Generator Module : This generates the following types of packets:
° SEND Packets
° RDMA Read Response Packets for all the Read Requests from the ERNIC IP
° ACK Packets for all the RDMA Write requests from the ERNIC IP
° RDMA READ and RDMA WRITE
• Example Design Features : RDMA READ and RDMA WRITE
• RX Checker Module : This module checks the capsules (from SEND packets) and payload (from Read Response) received from the ERNIC IP. This module also checks the number of door bells rang on the RQ side band interface. The payload size of Read Response packets, RDMA write requests is 256 bytes. Capsule size in the SEND packets is 80 bytes.
• WQE Generator Module : This is responsible for generating the work queue requests and SQ PI doorbell updates to the ERNIC IP.
• TX Checker Module : This checks the data transmitted by the ERNIC IP over the streaming interface.
• Initiator WQE Module : This fetches the data from DDR when RDMA READ occurs.
• Initiator Checker Modules :
° Data checker which checks the data received for RDMA WRITE operation.
° RDMA READ RESPONSE packet check for RDMA READ operation and ACK packet check for RDMA WRITE operation.