Example Design Limitations - Example Design Limitations - 4.0 English - PG332

Xilinx Embedded RDMA Enabled NIC LogiCORE IP Product Guide (PG332)
Document ID
PG332
Release Date
2022-12-02
Version
4.0 English

The ERNIC example design has the following limitations:

• Example design does not exercise Retry path

• Example design exercises only Hardware handshake path (QPCONFi[4] is set to 0 for all QPs)

• Example design does not exercise IPV6 packets

• Example design does not generate any connection management (MAD) packets to QP1

• Example design limits the number of each supported packet type transactions to 8