The following registers should be configured for ERNIC global configuration.
• Configuration of error buffers queue. Allocate memory and configure the base address to ERRBUFBA and queue depth and size to ERRBUFSZ registers. The register ERRBUFWPTR is used by the hardware to indicate the SW about the new entries in the ERROR buffer queue.
• Configure incoming packet error status queue. This queue gives the status of incoming packets with errors. To configure this queue, allocate memory and write the base address to IPKTERRQBA, queue depth and size to IPKTERRQSZ registers. IPKTERRQWPTR register is used by the hardware to indicate the SW about the new entries in the queue.
• Configure response error packet buffer. This involves writing memory base address to RESP_ERR_PKT_BUF_BA, queue depth and size to RESP_ERR_BUF_SZ and a DDR address to RESP_ERR_BUF_WRPTR for the hardware to indicate the SW about the response error buffer writes happened.
• Enable interrupts by writing to INTEN register.
• Allocate memory for CQ and RQ doorbells for all the QPs to be created. The doorbell memory for individual CQ and RQ are taken from offsets of this memory and configured in the corresponding ERNIC registers during the QP creation (see the QP1 Creation ).
• Configure source MAC address in the MACXADDLSB, MACXADDMSB registers.
• Configures source IP address. If the IP version is IPv6, then registers IPv6XADD1-4 are written with interface's IPv6 address, otherwise IPv4 address is written to IPv4XADD register.
• Configures number of QPs supported by the ERNIC design, UDP port and enables the ERNIC by writing to XRNICCONF register.