Core Overview - Core Overview - 4.0 English - PG332

Xilinx Embedded RDMA Enabled NIC LogiCORE IP Product Guide (PG332)

Document ID
PG332
Release Date
2022-12-02
Version
4.0 English

This chapter provides an overview of the ERNIC IP core and details of the applications, licensing requirements, and standards conformance. ERNIC is a soft IP implementing RDMA over a Converged Ethernet (RoCE v2) protocol for embedded target or initiator devices. This implementation is based on the specifications described in InfiniBand Architecture Specification Volume 1, Annex A16 RoCE and Annex 17 RoCE V2 [Ref 1] .

This Figure shows the ERNIC and its connections to other IPs in the subsystem.

Figure 1-1: ERNIC IP Block Diagram

X-Ref Target - Figure 1-1

X25376-ernic-block.jpg

Note: The user logic or target IP that connects to ERNIC is referred to as application and the direction of the arrows is from master to slave.

Apart from the ERNIC IP, the ERNIC subsystem includes the Xilinx Ethernet IP, AXI DMA, and AXI Interconnect among other IPs. On the user application front, the ERNIC IP exposes side band interfaces to allow efficient doorbell exchanges without going through the interconnect.

Each queue is identified with a set of read and write pointers called the Producer Index (write pointer) and Consumer Index (read pointer). The register address locations for these pointers are termed as doorbells in this document. A doorbell exchange or doorbell ringing indicates that the corresponding register location is updated.