Two clocks are exposed at the top of the ERNIC IP. These are: AXI4 clock and AXI4-Lite clock. All the registers accesses work on the AXI4-Lite clock while the rest of the logic works on AXI4 clock. Typically, the AXI4 clock would be of higher frequency (up to 200 MHz) while the AXI4-Lite interface could be clocked at a lower frequency (divided AXI4 clock with the divided clock edges aligning with the AXI4 clock). However, these clocks are treated as synchronous inside the ERNIC IP and are expected to be generated from the same clock source.