For comprehensive information about Vivado simulation components and information about using supported third-party tools, see the Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref 9] .
All required simulation sources are included for the core. Simulation of the QSGMII core at the core level is not supported without the addition of a test bench (not supplied). Simulation of the example design is supported.
IMPORTANT: For cores targeting 7 series or Zynq 7000 SoC devices, UNIFAST libraries are not supported. Xilinx IP is tested and qualified with UNISIM libraries only.