The QSGMII core is designed to integrate with the 7 series FPGA transceiver. This Figure illustrates the connections and logic required between the core and the transceiver; the signal names and logic in the figure precisely match those delivered with the example design when a 7 series FPGA transceiver is used.
The 125 MHz differential reference clock is routed directly to the 7 series transceiver. The transceiver is configured to output a version of this clock (125 MHz) on the txoutclk port; this is then placed onto global clock routing and passed to a MMCM which generates two clocks; one 125 MHz ( userclk2 ) and other 250 MHz ( userclk ). The userclk and userclk2 signals are input back into the GTPE2 transceiver on the user interface clock ports txusrclk and txusrclk2 . The userclk2 clock is also used to source for all core logic.
The transceiver is configured to output a recovered clock (250 MHz) on the rxoutclk port. This clock is divided down to 125 MHz using BUFR and is then used to source the receive logic from Transceiver receive side rxelastic buffer read in the core and rxusrclk2 port of transceiver. The 250 MHz rxoutclk is placed on regional clock routing using BUFR and is routed back to rxuserclk port of transceiver. The clocking logic is included in separate module, <component_name>_clocking , which is instantiated in the <component_name>_support module. In This Figure , clocking resources BUFMR and BUFR are used on rxoutclk . In certain devices BUFMRs are not available. In this case, other clocking schemes need to be used with the core generated with the Include Shared Logic in Example Design option.
The two wrapper files immediately around the GTP transceiver pair, gtwizard and gtwizard_gt ( This Figure ), are generated from the 7 series FPGA transceiver wizard. These files apply all the QSGMII attributes. Consequently, these files can be regenerated by invoking the 7 series FPGAs transceivers wizard in the Vivado Design Suite and selecting the QSGMII Protocol template on the Line Rate, RefClk Selection tab. For more information, see the 7 Series FPGAs GTP Transceivers User Guide (UG482) [Ref 6] .
Note: The optional Transceiver Control and Status ports are not shown here. These ports are brought up to the <component_name> module level.