Parameter Description |
Parameters |
Range |
Default
|
|||
---|---|---|---|---|---|---|
PSS Input frequency |
PSU__PSS_REF_CLK__FREQMHZ |
|
33.333 |
|||
PSU__PSS_ALT_REF_CLK__FREQMHZ |
|
33.333 |
||||
Video Ref Clk Frequency |
PSU__VIDEO_REF_CLK__FREQMHZ |
|
33.333 |
|||
PSU__AUX_REF_CLK__FREQMHZ |
|
33.333 |
||||
PSU__GT_REF_CLK__FREQMHZ |
|
33.333 |
||||
PSU__VIDEO_REF_CLK__ENABLE |
0,1 |
0 |
||||
PSU__VIDEO_REF_CLK__IO |
<Select>,MIO 27,MIO 50 |
<Select> |
||||
PSU__PSS_ALT_REF_CLK__ENABLE |
0,1 |
0 |
||||
PSU__PSS_ALT_REF_CLK__IO |
<Select>,MIO 28,MIO 51 |
<Select> |
||||
CAN Peripheral Related parameters |
PSU__CAN0__PERIPHERAL__ENABLE |
0,1 |
0 |
|||
PSU__CAN0__PERIPHERAL__IO |
<Select>,EMIO,MIO 2 .. 3,
|
<Select> |
||||
PSU__CAN0__GRP_CLK__ENABLE |
0,1 |
0 |
||||
CAN Peripheral Related parameters (continued)
|
PSU__CAN0__GRP_CLK__IO |
<Select>,MIO 0,MIO 1,MIO 2,
|
<Select> |
|||
PSU__CAN1__PERIPHERAL__ENABLE |
0,1 |
0 |
||||
PSU__CAN1__PERIPHERAL__IO |
<Select>,EMIO,MIO 0 .. 1,
|
<Select> |
||||
PSU__CAN1__GRP_CLK__ENABLE |
0,1 |
0 |
||||
CAN Peripheral Related parameters (continued) |
PSU__CAN1__GRP_CLK__IO |
<Select>,MIO 0,MIO 1,MIO 2,
|
<Select> |
|||
PSU__CAN0_LOOP_CAN1__ENABLE |
0,1 |
0 |
||||
PSU__DPAUX__PERIPHERAL__ENABLE |
0,1 |
0 |
||||
PSU__DPAUX__PERIPHERAL__IO |
<Select>,MIO 27 .. 30,
|
<Select> |
||||
ENET Related Parameters |
PSU__ENET0__GRP_MDIO__ENABLE |
0,1 |
0 |
|||
CONFIG.PSU__ENET0__FIFO__ENABLE |
|
0,1 |
0 |
|
||
CONFIG.PSU__ENET0__PTP__ENABLE |
|
0,1 |
0 |
|
||
PSU__ENET0__GRP_MDIO__IO |
<Select>,EMIO,MIO 76 .. 77 |
<Select> |
||||
PSU__GEM__TSU__ENABLE |
0,1 |
0 |
||||
PSU__GEM__TSU__IO |
<Select>,EMIO,MIO 26,
|
<Select> |
||||
PSU__ENET0__PERIPHERAL__ENABLE |
0,1 |
0 |
||||
PSU__ENET0__PERIPHERAL__IO |
<Select>,EMIO,GT Lane0,
|
<Select> |
||||
PSU__ENET1__PERIPHERAL__ENABLE |
0,1 |
0 |
||||
PSU__ENET1__PERIPHERAL__IO |
<Select>,EMIO,MIO 38 .. 49,
|
<Select> |
||||
PSU__ENET1__GRP_MDIO__ENABLE |
0,1 |
0 |
||||
PSU__ENET1__FIFO__ENABLE |
|
0,1 |
0 |
|
||
PSU__ENET1__PTP__ENABLE |
|
0,1 |
0 |
|
||
PSU__FPGA_PL0_ENABLE |
0,1 |
1 |
||||
PSU__FPGA_PL1_ENABLE |
0,1 |
0 |
||||
PSU__FPGA_PL2_ENABLE |
0,1 |
0 |
||||
PSU__FPGA_PL3_ENABLE |
0,1 |
0 |
||||
ENET Related Parameters (Continued) |
PSU__ENET1__GRP_MDIO__IO |
<Select>,EMIO,MIO 50 .. 51,
|
<Select> |
|||
PSU__ENET2__PERIPHERAL__ENABLE |
0,1 |
0 |
||||
PSU__ENET2__PERIPHERAL__IO |
<Select>,EMIO,GT Lane2,
|
<Select> |
||||
PSU__ENET2__GRP_MDIO__ENABLE |
0,1 |
0 |
||||
PSU__ENET2__FIFO__ENABLE |
|
0,1 |
0 |
|
||
PSU__ENET2__PTP__ENABLE |
|
0,1 |
0 |
|
||
PSU__ENET2__GRP_MDIO__IO |
<Select>,EMIO,MIO 76 .. 77 |
<Select> |
||||
PSU__ENET3__PERIPHERAL__ENABLE |
0,1 |
0 |
||||
PSU__ENET3__PERIPHERAL__IO |
<Select>,EMIO,GT Lane3,
|
<Select> |
||||
PSU__ENET3__GRP_MDIO__ENABLE |
0,1 |
0 |
||||
PSU__ENET3__FIFO__ENABLE |
|
0,1 |
0 |
|
||
PSU__ENET3__PTP__ENABLE |
|
0,1 |
0 |
|
||
PSU__ENET3__GRP_MDIO__IO |
<Select>,EMIO,MIO 76 .. 77 |
<Select> |
||||
GPIO Related Parameters |
PSU__GPIO_EMIO__PERIPHERAL__
|
0,1 |
0 |
|||
PSU__GPIO_EMIO__PERIPHERAL__IO |
<Select> |
<Select> |
||||
PSU__GPIO0_MIO__PERIPHERAL__
|
0,1 |
0 |
||||
PSU__GPIO0_MIO__IO |
<Select>,MIO 0 .. 25 |
<Select> |
||||
PSU__GPIO1_MIO__PERIPHERAL__
|
0,1 |
0 |
||||
PSU__GPIO1_MIO__IO |
<Select>,MIO 26 .. 51 |
<Select> |
||||
PSU__GPIO2_MIO__PERIPHERAL__
|
0,1 |
0 |
||||
PSU__GPIO2_MIO__IO |
<Select>,MIO 52 .. 77 |
<Select> |
||||
I2C Related Parameters |
PSU__I2C0__PERIPHERAL__ENABLE |
0,1 |
0 |
|||
PSU__I2C0__PERIPHERAL__IO |
<Select>,EMIO,MIO 2 .. 3,
|
<Select> |
||||
PSU__I2C0__GRP_INT__ENABLE |
0,1 |
0 |
||||
PSU__I2C0__GRP_INT__IO |
<Select> |
<Select> |
||||
PSU__I2C1__PERIPHERAL__ENABLE |
0,1 |
0 |
||||
I2C Related Parameters (continued) |
PSU__I2C1__PERIPHERAL__IO |
<Select>,EMIO,MIO 0 .. 1,
|
<Select> |
|||
PSU__I2C1__GRP_INT__ENABLE |
0,1 |
0 |
||||
PSU__I2C1__GRP_INT__IO |
<Select> |
<Select> |
||||
PSU__I2C0_LOOP_I2C1__ENABLE |
0,1 |
0 |
||||
PSU__TESTSCAN__PERIPHERAL__
|
0,1 |
0 |
||||
PCIE Peripheral Enable |
PSU__PCIE__PERIPHERAL__ENABLE |
0,1 |
0 |
|||
PSU__PCIE__PERIPHERAL__ENDPOINT_
|
0,1 |
1 |
||||
PSU__PCIE__PERIPHERAL__ROOTPORT_
|
0,1 |
0 |
||||
PSU__PCIE__PERIPHERAL__ENDPOINT_
|
<Select>,MIO 29,MIO 30,
|
<Select> |
||||
PSU__PCIE__PERIPHERAL__ROOTPORT_
|
<Select>,MIO 0,MIO 1,MIO 2,
|
<Select> |
||||
PCIE Lane Selections |
PSU__PCIE__LANE0__ENABLE |
0,1 |
0 |
|||
PSU__PCIE__LANE0__IO |
<Select>,GT Lane0 |
<Select> |
||||
PSU__PCIE__LANE1__ENABLE |
0,1 |
0 |
||||
PSU__PCIE__LANE1__IO |
<Select>,GT Lane1 |
<Select> |
||||
PSU__PCIE__LANE2__ENABLE |
0,1 |
0 |
||||
PSU__PCIE__LANE2__IO |
<Select>,GT Lane2 |
<Select> |
||||
PSU__PCIE__LANE3__ENABLE |
0,1 |
0 |
||||
PSU__PCIE__LANE3__IO |
<Select>,GT Lane3 |
<Select> |
||||
PSU__GT__LINK_SPEED |
<Select>,RBR,HBR,HBR2 |
<Select> |
||||
PSU__GT__VLT_SWNG_LVL_4 |
NA |
|
||||
PSU__GT__PRE_EMPH_LVL_4 |
NA |
|
||||
USB Related Parameters |
PSU__USB0__REF_CLK_SEL |
<Select>,Ref Clk0,Ref Clk1,
|
<Select> |
|||
PSU__USB0__REF_CLK_FREQ |
<Select>,26,52,100 |
<Select> |
||||
PSU__USB1__REF_CLK_SEL |
<Select>,Ref Clk0,Ref Clk1,
|
<Select> |
||||
PSU__USB1__REF_CLK_FREQ |
<Select>,26,52,100 |
<Select> |
||||
GEM Ref CLK |
PSU__GEM0__REF_CLK_SEL |
<Select>,Ref Clk0,Ref Clk1,
|
<Select> |
|||
PSU__GEM0__REF_CLK_FREQ |
<Select>,125 |
<Select> |
||||
PSU__GEM1__REF_CLK_SEL |
<Select>,Ref Clk0,Ref Clk1,
|
<Select> |
||||
PSU__GEM1__REF_CLK_FREQ |
<Select>,125 |
<Select> |
||||
PSU__GEM2__REF_CLK_SEL |
<Select>,Ref Clk0,Ref Clk1,
|
<Select> |
||||
PSU__GEM2__REF_CLK_FREQ |
<Select>,125 |
<Select> |
||||
PSU__GEM3__REF_CLK_SEL |
<Select>,Ref Clk0,Ref Clk1,
|
<Select> |
||||
PSU__GEM3__REF_CLK_FREQ |
<Select>,125 |
<Select> |
||||
DP Ref Clk |
PSU__DP__REF_CLK_SEL |
<Select>,Ref Clk0,Ref Clk1,
|
<Select> |
|||
PSU__DP__REF_CLK_FREQ |
<Select>,27,108,135 |
<Select> |
||||
SATA Ref Clk |
PSU__SATA__REF_CLK_SEL |
<Select>,Ref Clk0,Ref Clk1,
|
<Select> |
|||
PSU__SATA__REF_CLK_FREQ |
<Select>,150,125 |
<Select> |
||||
PCIE Ref Clk |
PSU__PCIE__REF_CLK_SEL |
<Select>,Ref Clk0,Ref Clk1,
|
<Select> |
|||
PSU__PCIE__REF_CLK_FREQ |
<Select>,100 |
<Select> |
||||
DP Lane Selection |
PSU__DP__LANE_SEL |
<Select>,Dual Higher,Dual Lower,Single Higher,Single Lower |
<Select> |
|||
PCIE Related Parameters |
PSU__PCIE__DEVICE_PORT_TYPE |
<Select>,Root Port,
|
<Select> |
|||
PSU__PCIE__MAXIMUM_LINK_WIDTH |
<Select>,x1,x2,x4 |
<Select> |
||||
PSU__PCIE__LINK_SPEED |
<Select>,2.5 Gb/s,5.0 Gb/s |
<Select> |
||||
PSU__PCIE__INTERFACE_WIDTH |
<Select>,64bit |
<Select> |
||||
PSU__PCIE__BAR0_ENABLE |
0,1 |
0 |
||||
PSU__PCIE__BAR0_TYPE |
<Select>,Memory,IO |
<Select> |
||||
PSU__PCIE__BAR0_SCALE |
<Select>,Bytes,Kilobytes,
|
<Select> |
||||
PSU__PCIE__BAR0_64BIT |
0,1 |
0 |
||||
PSU__PCIE__BAR0_SIZE |
<Select>,1,2,4,8,16,32,64,128,
|
<Select> |
||||
PSU__PCIE__BAR0_VAL |
NA |
|
||||
PSU__PCIE__BAR0_PREFETCHABLE |
0,1 |
0 |
||||
PSU__PCIE__BAR1_ENABLE |
0,1 |
0 |
||||
PSU__PCIE__BAR1_TYPE |
<Select>,Memory,IO |
<Select> |
||||
PSU__PCIE__BAR1_SCALE |
<Select>,Bytes,Kilobytes,
|
<Select> |
||||
PSU__PCIE__BAR1_64BIT |
0,1 |
0 |
||||
PSU__PCIE__BAR1_SIZE |
<Select>,1,2,4,8,16,32,64,128,
|
<Select> |
||||
PSU__PCIE__BAR1_VAL |
NA |
|
||||
PSU__PCIE__BAR1_PREFETCHABLE |
0,1 |
0 |
||||
PSU__PCIE__BAR2_ENABLE |
0,1 |
0 |
||||
PSU__PCIE__BAR2_TYPE |
<Select>,Memory |
<Select> |
||||
PSU__PCIE__BAR2_SCALE |
<Select>,Bytes,Kilobytes,
|
<Select> |
||||
PSU__PCIE__BAR2_64BIT |
0,1 |
0 |
||||
PSU__PCIE__BAR2_SIZE |
<Select>,1,2,4,8,16,32,64,128,
|
<Select> |
||||
|
PSU__PCIE__BAR2_VAL |
NA |
|
|||
PSU__PCIE__BAR2_PREFETCHABLE |
0,1 |
0 |
||||
PSU__PCIE__BAR3_ENABLE |
0,1 |
0 |
||||
PCIE Related Parameters (continued) |
PSU__PCIE__BAR3_TYPE |
<Select>,Memory |
<Select> |
|||
PSU__PCIE__BAR3_SCALE |
<Select>,Bytes,Kilobytes,
|
<Select> |
||||
PSU__PCIE__BAR3_64BIT |
0,1 |
0 |
||||
PSU__PCIE__BAR3_SIZE |
<Select>,1,2,4,8,16,32,64,128,
|
<Select> |
||||
PSU__PCIE__BAR3_VAL |
NA |
|
||||
PSU__PCIE__BAR3_PREFETCHABLE |
0,1 |
0 |
||||
PSU__PCIE__BAR4_ENABLE |
0,1 |
0 |
||||
PSU__PCIE__BAR4_TYPE |
<Select>,Memory |
<Select> |
||||
PSU__PCIE__BAR4_SCALE |
<Select>,Bytes,Kilobytes,
|
<Select> |
||||
PSU__PCIE__BAR4_64BIT |
0,1 |
0 |
||||
PSU__PCIE__BAR4_SIZE |
<Select>,1,2,4,8,16,32,64,128,
|
<Select> |
||||
PSU__PCIE__BAR4_VAL |
NA |
|
||||
PSU__PCIE__BAR4_PREFETCHABLE |
0,1 |
0 |
||||
PSU__PCIE__BAR5_ENABLE |
0,1 |
0 |
||||
PSU__PCIE__BAR5_TYPE |
<Select>,Memory |
<Select> |
||||
PSU__PCIE__BAR5_SCALE |
<Select>,Bytes,Kilobytes,
|
<Select> |
||||
PSU__PCIE__BAR5_64BIT |
0,1 |
0 |
||||
PSU__PCIE__BAR5_SIZE |
<Select>,1,2,4,8,16,32,64,128,
|
<Select> |
||||
PSU__PCIE__BAR5_VAL |
NA |
|
||||
PSU__PCIE__BAR5_PREFETCHABLE |
0,1 |
0 |
||||
PSU__PCIE__EROM_ENABLE |
0,1 |
0 |
||||
PCIE Related Parameters (continued) |
PSU__PCIE__EROM_SCALE |
<Select>,Kilobytes,Megabytes,
|
<Select> |
|||
PSU__PCIE__EROM_SIZE |
<Select>,2,4,8,16,32,64,128,256,
|
<Select> |
||||
PSU__PCIE__EROM_VAL |
NA |
|
||||
PSU__PCIE__CAP_SLOT_IMPLEMENTED |
<Select> |
<Select> |
||||
PSU__PCIE__MAX_PAYLOAD_SIZE |
<Select>,128 bytes,256 bytes |
<Select> |
||||
PSU__PCIE__LEGACY_INTERRUPT |
<Select> |
<Select> |
||||
PSU__PCIE__VENDOR_ID |
NA |
|
||||
PSU__PCIE__DEVICE_ID |
NA |
|
||||
PSU__PCIE__REVISION_ID |
NA |
|
||||
PSU__PCIE__SUBSYSTEM_VENDOR_ID |
NA |
|
||||
PSU__PCIE__SUBSYSTEM_ID |
NA |
|
||||
PSU__PCIE__BASE_CLASS_MENU |
See Note (1) for values
|
<Select> |
||||
PSU__PCIE__USE_CLASS_CODE_LOOKUP_ASSISTANT |
<Select>,0,1 |
<Select> |
||||
PSU__PCIE__SUB_CLASS_INTERFACE_
|
<Select>,
|
<Select> |
||||
PSU__PCIE__CLASS_CODE_BASE |
NA |
|
||||
PSU__PCIE__CLASS_CODE_SUB |
NA |
|
||||
PSU__PCIE__CLASS_CODE_INTERFACE |
NA |
|
||||
PSU__PCIE__CLASS_CODE_VALUE |
NA |
|
||||
PSU__PCIE__AER_CAPABILITY |
0,1 |
0 |
||||
PSU__PCIE__CORRECTABLE_INT_ERR |
0,1 |
0 |
||||
PSU__PCIE__HEADER_LOG_OVERFLOW |
0,1 |
0 |
||||
PSU__PCIE__RECEIVER_ERR |
0,1 |
0 |
||||
PSU__PCIE__SURPRISE_DOWN |
0,1 |
0 |
||||
PCIE Related Parameters (continued) |
PSU__PCIE__FLOW_CONTROL_ERR |
0,1 |
0 |
|||
PSU__PCIE__COMPLTION_TIMEOUT |
0,1 |
0 |
||||
PSU__PCIE__COMPLETER_ABORT |
0,1 |
0 |
||||
PSU__PCIE__RECEIVER_OVERFLOW |
0,1 |
0 |
||||
PSU__PCIE__ECRC_ERR |
0,1 |
0 |
||||
PSU__PCIE__ACS_VIOLAION |
NA |
NA |
||||
PSU__PCIE__UNCORRECTABL_INT_ERR |
0,1 |
0 |
||||
PSU__PCIE__MC_BLOCKED_TLP |
0,1 |
0 |
||||
PSU__PCIE__ATOMICOP_EGRESS_BLOCKED |
0,1 |
0 |
||||
PSU__PCIE__TLP_PREFIX_BLOCKED |
0,1 |
0 |
||||
PSU__PCIE__FLOW_CONTROL_
|
0,1 |
0 |
||||
PSU__PCIE__ACS_VIOLATION |
0,1 |
0 |
||||
PSU__PCIE__MULTIHEADER |
0,1 |
0 |
||||
PSU__PCIE__ECRC_CHECK |
0,1 |
0 |
||||
PSU__PCIE__ECRC_GEN |
0,1 |
0 |
||||
PSU__PCIE__PERM_ROOT_ERR_
|
0,1 |
0 |
||||
PSU__PCIE__CRS_SW_VISIBILITY |
0,1 |
0 |
||||
PSU__PCIE__INTX_GENERATION |
0,1 |
0 |
||||
PSU__PCIE__INTX_PIN |
<Select>,INTA |
<Select> |
||||
PSU__PCIE__MSI_CAPABILITY |
0,1 |
0 |
||||
PSU__PCIE__MSI_64BIT_ADDR_
|
0,1 |
0 |
||||
PSU__PCIE__MSI_MULTIPLE_MSG_
|
<Select>,1 Vector,2 Vector,
|
<Select> |
||||
PSU__PCIE__MSIX_CAPABILITY |
0,1 |
0 |
||||
PSU__PCIE__MSIX_TABLE_SIZE |
NA |
0 |
||||
PSU__PCIE__MSIX_TABLE_OFFSET |
NA |
0 |
||||
PSU__PCIE__MSIX_BAR_INDICATOR |
NA |
|
||||
PSU__PCIE__MSIX_PBA_OFFSET |
NA |
0 |
||||
PSU__PCIE__MSIX_PBA_BAR_
|
NA |
|
||||
PCIE Related Parameters (continued) |
PSU__PCIE__BRIDGE_BAR_INDICATOR |
<Select>,BAR 0,BAR 1,BAR 2,
|
<Select> |
|||
PSU_IMPORT_BOARD_PRESET |
NA |
|
||||
Isolation & protection related parameters |
PSU__PROTECTION__SUBSYSTEMS |
|
PMU Firmware: PU |
|||
PSU__PROTECTION__MASTERS_TZ |
|
None |
||||
PSU__PROTECTION__MASTERS |
|
See
Table: PSU__PROTECTION__MASTERS Default Values
|
||||
PSU__PROTECTION__DDR_SEGMENTS |
|
None |
||||
PSU__PROTECTION__OCM_SEGMENTS |
|
None |
||||
PSU__PROTECTION__LPD_SEGMENTS |
|
None |
||||
PSU__PROTECTION__FPD_SEGMENTS |
|
None |
||||
PSU__PROTECTION__DEBUG |
|
1 |
||||
PSU__PROTECTION__SLAVES |
|
See
Table: PSU__PROTECTION__SLAVES
|
||||
PSU__PROTECTION__PRESUBSYSTEMS |
|
None |
||||
PSU__PROTECTION__ENABLE |
|
|
|
False |
|
|
PSU__PROTECTION__LOCK_UNUSED_SEGMENTS |
|
|
|
0 |
|
|
Internal Parameter |
PSU__EP__IP |
0,1 |
0 |
|||
PSU__ACTUAL__IP |
0,1 |
1 |
||||
Nand Related Parameters |
PSU__NAND__PERIPHERAL__IO |
<Select>,MIO 13 .. 25 |
<Select> |
|||
PSU__NAND__PERIPHERAL__ENABLE |
0,1 |
0 |
||||
PSU__NAND__READY_BUSY__ENABLE |
0,1 |
0 |
||||
PSU__NAND__READY_BUSY__IO |
<Select>,MIO 10 .. 11,MIO 27 .. 28 |
<Select> |
||||
PSU__NAND__CHIP_ENABLE__ENABLE |
0,1 |
0 |
||||
PSU__NAND__CHIP_ENABLE__IO |
<Select>,MIO 9,MIO 26 |
<Select> |
||||
PSU__NAND__DATA_STROBE__ENABLE |
0,1 |
0 |
||||
PSU__NAND__DATA_STROBE__IO |
<Select>,MIO 12,MIO 32 |
<Select> |
||||
PSU__PJTAG__PERIPHERAL__ENABLE |
0,1 |
0 |
||||
PSU__PJTAG__PERIPHERAL__IO |
<Select>,MIO 0 .. 3,
|
<Select> |
||||
PMU related Parameters |
PSU__PMU__PERIPHERAL__ENABLE |
0,1 |
0 |
|||
PSU__PMU__PERIPHERAL__IO |
<Select> |
<Select> |
||||
PSU__PMU__EMIO_GPI__ENABLE (4) |
0,1 |
0 |
||||
PSU__PMU__EMIO_GPO__ENABLE |
0,1 |
0 |
||||
PSU__PMU__GPI0__ENABLE |
0,1 |
0 |
||||
PSU__PMU__GPI1__ENABLE |
0,1 |
0 |
||||
PSU__PMU__GPI2__ENABLE |
0,1 |
0 |
||||
PSU__PMU__GPI3__ENABLE |
0,1 |
0 |
||||
PSU__PMU__GPI4__ENABLE |
0,1 |
0 |
||||
PSU__PMU__GPI5__ENABLE |
0,1 |
0 |
||||
PSU__PMU__GPO0__ENABLE |
0,1 |
0 |
||||
PSU__PMU__GPO1__ENABLE |
0,1 |
0 |
||||
PSU__PMU__GPO2__ENABLE |
0,1 |
0 |
||||
PSU__PMU__GPO3__ENABLE |
0,1 |
0 |
||||
PSU__PMU__GPO4__ENABLE |
0,1 |
0 |
||||
PSU__PMU__GPO5__ENABLE |
0,1 |
0 |
||||
PSU__PMU__GPI0__IO (5) |
<Select>,MIO 26 |
<Select> |
||||
PSU__PMU__GPI1__IO |
<Select>,MIO 27 |
<Select> |
||||
PSU__PMU__GPI2__IO |
<Select>,MIO 28 |
<Select> |
||||
PSU__PMU__GPI3__IO |
<Select>,MIO 29 |
<Select> |
||||
PSU__PMU__GPI4__IO |
<Select>,MIO 30 |
<Select> |
||||
PSU__PMU__GPI5__IO |
<Select>,MIO 31 |
<Select> |
||||
PSU__PMU__GPO0__IO (6) |
<Select>,MIO 32 |
<Select> |
||||
PSU__PMU__GPO1__IO |
<Select>,MIO 33 |
<Select> |
||||
PSU__PMU__GPO2__IO |
<Select>,MIO 34 |
<Select> |
||||
PSU__PMU__GPO3__IO |
<Select>,MIO 35 |
<Select> |
||||
PSU__PMU__GPO4__IO |
<Select>,MIO 36 |
<Select> |
||||
PSU__PMU__GPO5__IO |
<Select>,MIO 37 |
<Select> |
||||
CONFIG.PSU__PMU__AIBACK__ENABLE |
|
0,1 |
|
0 |
|
|
CONFIG.PSU__PMU__PLERROR__ENABLE |
|
0,1 |
|
0 |
|
|
CSU |
PSU__CSU__PERIPHERAL__ENABLE |
0,1 |
0 |
|||
PSU__CSU__PERIPHERAL__IO |
<Select>,MIO 18,MIO 19,
|
<Select> |
||||
QSPI Related Parameters |
PSU__QSPI__PERIPHERAL__ENABLE |
0,1 |
0 |
|||
PSU__QSPI__PERIPHERAL__IO |
<Select>,MIO 0 .. 5,MIO 0 .. 7,
|
<Select> |
||||
PSU__QSPI__PERIPHERAL__MODE |
<Select>,Single,Dual Stacked,
|
<Select> |
||||
PSU__QSPI__PERIPHERAL__DATA_MODE |
<Select>,x1,x2,x4 |
<Select> |
||||
PSU__QSPI__GRP_FBCLK__ENABLE |
0,1 |
0 |
||||
PSU__QSPI__GRP_FBCLK__IO |
<Select>,MIO 6 |
<Select> |
||||
SD Related Parameters |
PSU__SD0__PERIPHERAL__ENABLE |
0,1 |
0 |
|||
PSU__SD0__PERIPHERAL__IO |
<Select>,EMIO,
|
<Select> |
||||
PSU__SD0__GRP_CD__ENABLE |
0,1 |
0 |
||||
PSU__SD0__GRP_CD__IO |
<Select>,EMIO,MIO 24,
|
<Select> |
||||
PSU__SD0__GRP_POW__ENABLE |
0,1 |
0 |
||||
PSU__SD0__GRP_POW__IO |
<Select>,EMIO,MIO 23,
|
<Select> |
||||
PSU__SD0__GRP_WP__ENABLE |
0,1 |
0 |
||||
PSU__SD0__GRP_WP__IO |
<Select>,EMIO,MIO 25,
|
<Select> |
||||
PSU__SD0__SLOT_TYPE |
<Select>,SD 2.0,SD 3.0, SD 3.0 AUTODIR, eMMC |
<Select> |
||||
PSU__SD0__RESET__ENABLE |
0,1 |
0 |
||||
PSU__SD0__DATA_TRANSFER_MODE |
<Select>,4Bit,8Bit |
<Select> |
||||
SD Related Parameters (cont’d ) |
PSU__SD0__CLK_50_SDR_ITAP_DLY |
|
0x0-0xb3 |
0x0 |
|
|
PSU__SD0__CLK_50_SDR_OTAP_DLY |
|
0x0-0x2c |
0x0 |
|
||
PSU__SD0__CLK_50_DDR_ITAP_DLY |
|
0x0-0xb3 |
0x0 |
|
||
PSU__SD0__CLK_50_DDR_OTAP_DLY |
|
0x0-0x2c |
0x0 |
|
||
PSU__SD0__CLK_100_SDR_OTAP_DLY |
|
0x0-0x2c |
0x0 |
|
||
PSU__SD0__CLK_200_SDR_OTAP_DLY |
|
0x0-0x2c |
0x0 |
|
||
PSU__SD1__CLK_50_SDR_ITAP_DLY |
|
0x0-0xb3 |
|
|
||
PSU__SD1__CLK_50_SDR_OTAP_DLY |
|
0x0-0x2c |
0x0 |
|
||
PSU__SD1__CLK_50_DDR_ITAP_DLY |
|
0x0-0xb3 |
0x0 |
|
||
PSU__SD1__CLK_50_DDR_OTAP_DLY |
|
0x0-0x2c |
0x0 |
|
||
PSU__SD1__CLK_100_SDR_OTAP_DLY |
|
0x0-0x2c |
0x0 |
|
||
PSU__SD1__CLK_200_SDR_OTAP_DLY |
|
0x0-0x2c |
0x0 |
|
||
PSU__SD1__PERIPHERAL__ENABLE |
0,1 |
0 |
||||
PSU__SD1__PERIPHERAL__IO |
<Select>,EMIO,MIO 39 .. 51,
|
<Select> |
||||
PSU__SD1__GRP_CD__ENABLE |
0,1 |
0 |
||||
PSU__SD1__GRP_CD__IO |
<Select>,MIO 45,MIO 77,EMIO |
<Select> |
||||
PSU__SD1__GRP_POW__ENABLE |
0,1 |
0 |
||||
PSU__SD1__GRP_POW__IO |
<Select>,MIO 43,MIO 70,EMIO |
<Select> |
||||
PSU__SD1__GRP_WP__ENABLE |
0,1 |
0 |
||||
PSU__SD1__GRP_WP__IO |
<Select>,MIO 44,MIO 69,EMIO |
<Select> |
||||
PSU__SD1__SLOT_TYPE |
<Select>,SD 2.0,SD 3.0, SD 3.0 AUTODIR, eMMC |
<Select> |
||||
PSU__SD1__RESET__ENABLE |
0,1 |
0 |
||||
PSU__SD1__DATA_TRANSFER_MODE |
<Select>,4Bit,8Bit |
<Select> |
||||
Internal Parameter |
PSU__DEVICE_TYPE |
EG,CG,EV |
EG |
|||
SPI Related Parameters |
PSU__SPI0__PERIPHERAL__ENABLE |
0,1 |
0 |
|||
PSU__SPI0__PERIPHERAL__IO |
<Select>,EMIO,MIO 0 .. 5,
|
<Select> |
||||
PSU__SPI0__GRP_SS0__ENABLE |
0,1 |
0 |
||||
PSU__SPI0__GRP_SS0__IO |
<Select>,MIO 3,MIO 15,
|
<Select> |
||||
PSU__SPI0__GRP_SS1__ENABLE |
0,1 |
0 |
||||
PSU__SPI0__GRP_SS1__IO |
<Select>,MIO 2,MIO 14,
|
<Select> |
||||
PSU__SPI0__GRP_SS2__ENABLE |
0,1 |
0 |
||||
PSU__SPI0__GRP_SS2__IO |
<Select>,MIO 1,MIO 13,
|
<Select> |
||||
PSU__SPI1__PERIPHERAL__ENABLE |
0,1 |
0 |
||||
PSU__SPI1__PERIPHERAL__IO |
<Select>,EMIO,MIO 6 .. 11,
|
<Select> |
||||
PSU__SPI1__GRP_SS0__ENABLE |
0,1 |
0 |
||||
PSU__SPI1__GRP_SS0__IO |
<Select>,MIO 9,MIO 21,
|
<Select> |
||||
PSU__SPI1__GRP_SS1__ENABLE |
0,1 |
0 |
||||
PSU__SPI1__GRP_SS1__IO |
<Select>,MIO 8,MIO 20,
|
<Select> |
||||
PSU__SPI1__GRP_SS2__ENABLE |
0,1 |
0 |
||||
PSU__SPI1__GRP_SS2__IO |
<Select>,MIO 7,MIO 19,
|
<Select> |
||||
PSU__SPI0_LOOP_SPI1__ENABLE |
0,1 |
0 |
||||
SWDT Related parameters |
PSU__SWDT0__PERIPHERAL__ENABLE |
0,1 |
0 |
|||
PSU__SWDT0__CLOCK__ENABLE |
0,1 |
0 |
||||
PSU__SWDT0__RESET__ENABLE |
0,1 |
0 |
||||
PSU__SWDT0__PERIPHERAL__IO |
NA |
NA |
||||
PSU__SWDT0__CLOCK__IO |
<Select>,EMIO,MIO 6,MIO 10,
|
<Select> |
||||
PSU__SWDT0__RESET__IO |
<Select>,EMIO,MIO 7,MIO 11,
|
<Select> |
||||
PSU__SWDT1__PERIPHERAL__ENABLE |
0,1 |
0 |
||||
PSU__SWDT1__CLOCK__ENABLE |
0,1 |
0 |
||||
PSU__SWDT1__RESET__ENABLE |
0,1 |
0 |
||||
PSU__SWDT1__PERIPHERAL__IO |
NA |
NA |
||||
PSU__SWDT1__CLOCK__IO |
<Select>,EMIO,MIO 4,MIO 8,
|
<Select> |
||||
PSU__SWDT1__RESET__IO |
<Select>,EMIO,MIO 5,MIO 9,
|
<Select> |
||||
UART Baud rate |
PSU__UART0__BAUD_RATE |
<Select>,110,300,1200,2400,4800,9600,19200,38400,57600,115200,
|
<Select> |
|||
Trace Related Parameters |
PSU__TRACE__PERIPHERAL__ENABLE |
0,1 |
0 |
|||
PSU__TRACE__PERIPHERAL__IO |
<Select>,MIO 0 .. 17,
|
<Select> |
||||
PSU__TRACE__WIDTH |
<Select>,2Bit,4Bit,8Bit,16Bit,32Bit |
<Select> |
||||
PSU__TRACE__INTERNAL_WIDTH |
2,4,8,16,32 |
32 |
||||
TTC Related Parameters |
PSU__TTC0__PERIPHERAL__ENABLE |
0,1 |
0 |
|||
PSU__TTC0__CLOCK__ENABLE |
0,1 |
0 |
||||
PSU__TTC0__WAVEOUT__ENABLE |
0,1 |
0 |
||||
PSU__TTC0__CLOCK__IO |
<Select>,EMIO,MIO 6,MIO 14,
|
<Select> |
||||
PSU__TTC0__WAVEOUT__IO |
<Select>,EMIO,MIO 7,MIO 15,
|
<Select> |
||||
PSU__TTC0__PERIPHERAL__IO |
NA |
NA |
||||
PSU__TTC1__PERIPHERAL__ENABLE |
0,1 |
0 |
||||
PSU__TTC1__PERIPHERAL__IO |
NA |
NA |
||||
UART Baud rate |
PSU__UART1__BAUD_RATE |
<Select>,110,300,1200,2400,4800,9600,19200,38400,57600,115200,
|
<Select> |
|||
TTC Related Parameters |
PSU__TTC1__CLOCK__ENABLE |
0,1 |
0 |
|||
PSU__TTC1__WAVEOUT__ENABLE |
0,1 |
0 |
||||
PSU__TTC1__CLOCK__IO |
<Select>,EMIO,MIO 4,MIO 12,
|
<Select> |
||||
PSU__TTC1__WAVEOUT__IO |
<Select>,EMIO,MIO 5,MIO 13,
|
<Select> |
||||
PSU__TTC2__PERIPHERAL__ENABLE |
0,1 |
0 |
||||
PSU__TTC2__PERIPHERAL__IO |
NA |
NA |
||||
PSU__TTC2__CLOCK__ENABLE |
0,1 |
0 |
||||
PSU__TTC2__WAVEOUT__ENABLE |
0,1 |
0 |
||||
PSU__TTC2__CLOCK__IO |
<Select>,EMIO,MIO 2,MIO 10,
|
<Select> |
||||
PSU__TTC2__WAVEOUT__IO |
<Select>,EMIO,MIO 3,MIO 11,
|
<Select> |
||||
PSU__TTC3__PERIPHERAL__ENABLE |
0,1 |
0 |
||||
PSU__TTC3__PERIPHERAL__IO |
NA |
NA |
||||
PSU__TTC3__CLOCK__ENABLE |
0,1 |
0 |
||||
PSU__TTC3__WAVEOUT__ENABLE |
0,1 |
0 |
||||
TTC Related Parameters (continued) |
PSU__TTC3__CLOCK__IO |
<Select>,EMIO,MIO 0,MIO 8,MIO 16,MIO 24,MIO 32,MIO 40,MIO 48,MIO 56,MIO 64 |
<Select> |
|||
PSU__TTC3__WAVEOUT__IO |
<Select>,EMIO,MIO 1,MIO 9,MIO 17,MIO 25,MIO 33,MIO 41,MIO 49,MIO 57,MIO 65 |
<Select> |
||||
DDR Related Parameters |
PSU__DDRC__AL |
|
0 |
|||
PSU__DDRC__BANK_ADDR_COUNT |
|
3 |
||||
PSU__DDRC__BUS_WIDTH |
32 Bit,64 Bit |
64 Bit |
||||
DDR Related Parameters (Continued) |
PSU__DDRC__CL |
NA |
7 |
|||
PSU__DDRC__CLOCK_STOP_EN |
0,1 |
0 |
||||
PSU__DDRC__COL_ADDR_COUNT |
|
10 |
||||
PSU__DDRC__RANK_ADDR_COUNT |
|
0 |
||||
PSU__DDRC__CWL |
NA |
7 |
||||
PSU__DDRC__BG_ADDR_COUNT |
1.000000,2.000000 |
NA |
||||
PSU__DDRC__DEVICE_CAPACITY |
512 MBits,1024 MBits,2048 MBits,4096 MBits,8192 MBits |
2048 MBits |
||||
PSU__DDRC__DRAM_WIDTH |
8 Bits,16 Bits |
8 Bits |
||||
PSU__DDRC__ECC |
Disabled,Enabled |
Disabled |
||||
PSU__DDRC__ECC_SCRUB |
0,1 |
0 |
||||
PSU__DDRC__ENABLE |
0,1 |
1 |
||||
PSU__DDRC__FREQ_MHZ |
-2,-1 |
1 |
||||
PSU__DDRC__HIGH_TEMP |
<Select> |
<Select> |
||||
PSU__DDRC__MEMORY_TYPE |
LPDDR 3,DDR 3,
|
DDR 4 |
||||
PSU__DDRC__PARTNO |
<Select> |
<Select> |
||||
PSU__DDRC__ROW_ADDR_COUNT |
-2,-1 |
15 |
||||
PSU__DDRC__SPEED_BIN |
DDR3_800D,DDR3_800E,
|
DDR4_1600J |
||||
PSU__DDRC__T_FAW |
-0.1,100 |
35 |
||||
PSU__DDRC__T_RAS_MIN |
-0.1,100 |
35 |
||||
PSU__DDRC__T_RC |
-0.1,100 |
47.5 |
||||
DDR Related Parameters (continued) |
PSU__DDRC__T_RCD |
-2,-1 |
10 |
|||
PSU__DDRC__T_RP |
-0.1,100 |
10 |
||||
PSU__DDRC__TRAIN_DATA_EYE |
0,1 |
1 |
||||
PSU__DDRC__TRAIN_READ_GATE |
0,1 |
1 |
||||
PSU__DDRC__TRAIN_WRITE_LEVEL |
0,1 |
1 |
||||
PSU__DDRC__VREF |
0,1 |
1 |
||||
PSU__DDRC__VIDEO_BUFFER_SIZE |
0,1,2,4,8,16,32 |
0 |
||||
PSU__DDRC__BRC_MAPPING |
ROW_BANK_COL,BANK_ROW_COL |
ROW_BANK_COL |
||||
PSU__DDRC__DIMM_ADDR_MIRROR |
0,1 |
0 |
||||
PSU__DDRC__STATIC_RD_MODE |
0,1 |
0 |
||||
PSU__DDRC__DDR4_MAXPWR_SAVING_EN |
0,1 |
NA |
||||
PSU__DDRC__PWR_DOWN_EN |
0,1 |
0 |
||||
PSU__DDRC__DEEP_PWR_DOWN_EN |
<Select>,0,1 |
<Select> |
||||
PSU__DDRC__PLL_BYPASS |
0,1 |
0 |
||||
PSU__DDRC__DDR4_T_REF_MODE |
0,1 |
NA |
||||
PSU__DDRC__DDR4_T_REF_RANGE |
Normal (0-85),High (95 Max) |
NA |
||||
PSU__DDRC__PHY_DBI_MODE |
0,1 |
0 |
||||
PSU__DDRC__DM_DBI |
NO_DM_NO_DBI,
|
DM_NO_
|
||||
PSU__DDRC__COMPONENTS |
Components,UDIMM,RDIMM |
Components |
||||
PSU__DDRC__PARITY_ENABLE |
0,1 |
NA |
||||
PSU__DDRC__DDR4_CAL_MODE_
|
0,1 |
NA |
||||
PSU__DDRC__DDR4_CRC_CONTROL |
0,1 |
NA |
||||
PSU__DDRC__FGRM |
1X,2X,4X |
1X |
||||
PSU__DDRC__VENDOR_PART |
OTHERS,SAMSUNG,HYNIX |
OTHERS |
||||
DDR Related Parameters (continued)
|
PSU__DDRC__SB_TARGET |
5-5-5,6-6-6,7-7-7,8-8-8,9-9-9,
|
10-10-10 |
|||
PSU__DDRC__LP_ASR |
manual normal,
|
manual normal |
||||
PSU__DDRC__DDR4_ADDR_MAPPING |
0,1 |
NA |
||||
PSU__DDRC__SELF_REF_ABORT |
0,1 |
0 |
||||
PSU__DDRC__DERATE_INT_D |
<Select> |
<Select> |
||||
PSU__DDRC__ADDR_MIRROR |
0,NA,1 |
NA |
||||
PSU__DDRC__EN_2ND_CLK |
0,1 |
0 |
||||
PSU__DDRC__PER_BANK_REFRESH |
0,1 |
0 |
||||
PSU_DDR_RAM_HIGHADDR |
NA |
0x1FFFFFFF |
||||
CONFIG.PSU__DDR_SW_REFRESH_ENABLED |
|
0,1 |
1 |
|
||
Full Power Domain ON |
PSU__FP__POWER__ON |
0,1 |
1 |
|||
PL Power ON |
PSU__PL__POWER__ON |
0,1 |
1 |
|||
OCM Bank
|
PSU__OCM_BANK0__POWER__ON |
0,1 |
1 |
|||
PSU__OCM_BANK1__POWER__ON |
0,1 |
1 |
||||
PSU__OCM_BANK2__POWER__ON |
0,1 |
1 |
||||
PSU__OCM_BANK3__POWER__ON |
0,1 |
1 |
||||
TCM Power On |
PSU__TCM0A__POWER__ON |
0,1 |
1 |
|||
PSU__TCM0B__POWER__ON |
0,1 |
1 |
||||
PSU__TCM1A__POWER__ON |
0,1 |
1 |
||||
PSU__TCM1B__POWER__ON |
0,1 |
1 |
||||
RPU Power ON |
PSU__RPU__POWER__ON |
0,1 |
1 |
|||
PSU__L2_BANK0__POWER__ON |
0,1 |
1 |
||||
PSU__GPU_PP0__POWER__ON |
0,1 |
1 |
||||
PSU__GPU_PP1__POWER__ON |
0,1 |
1 |
||||
PSU__ACPU0__POWER__ON |
0,1 |
1 |
||||
PSU__ACPU1__POWER__ON |
0,1 |
1 |
||||
PSU__ACPU2__POWER__ON |
0,1 |
1 |
||||
PSU__ACPU3__POWER__ON |
0,1 |
1 |
||||
UART Related Parameters |
PSU__UART0__PERIPHERAL__ENABLE |
0,1 |
0 |
|||
PSU__UART0__PERIPHERAL__IO |
<Select>,EMIO,MIO 2 .. 3,
|
<Select> |
||||
PSU__UART0__MODEM__ENABLE |
0,1 |
0 |
||||
PSU__UART1__PERIPHERAL__ENABLE |
0,1 |
0 |
||||
UART Related Parameters (continued) |
PSU__UART1__PERIPHERAL__IO |
<Select>,EMIO,MIO 0 .. 1,
|
<Select> |
|||
PSU__UART1__MODEM__ENABLE |
0,1 |
0 |
||||
PSU__UART0_LOOP_UART1__ENABLE |
0,1 |
0 |
||||
USB Related Parameters |
PSU__USB0__PERIPHERAL__ENABLE |
0,1 |
0 |
|||
PSU__USB0__PERIPHERAL__IO |
<Select>,MIO 52 .. 63 |
<Select> |
||||
PSU__USB1__PERIPHERAL__ENABLE |
0,1 |
0 |
||||
PSU__USB1__PERIPHERAL__IO |
<Select>,MIO 64 .. 75 |
<Select> |
||||
PSU__USB3_0__PERIPHERAL__ENABLE |
0,1 |
0 |
||||
PSU__USB3_0__PERIPHERAL__IO |
<Select>,GT Lane0,GT Lane1,
|
<Select> |
||||
PSU__USB3_1__PERIPHERAL__ENABLE |
0,1 |
0 |
||||
PSU__USB3_1__PERIPHERAL__IO |
<Select>,GT Lane3 |
<Select> |
||||
PSU__USB3_0__EMIO__ENABLE |
0,1 |
0 |
||||
PSU__USB2_0__EMIO__ENABLE |
0,1 |
0 |
||||
PSU__USB3_1__EMIO__ENABLE |
0,1 |
0 |
||||
PSU__USB2_1__EMIO__ENABLE |
0,1 |
0 |
||||
PS PL Interface related Parameters |
PSU__USE__M_AXI_GP0 |
0,1 |
0 |
|||
PSU__MAXIGP0__DATA_WIDTH |
128,64,32 |
128 |
||||
PSU__USE__M_AXI_GP1 |
0,1 |
0 |
||||
PSU__MAXIGP1__DATA_WIDTH |
128,64,32 |
128 |
||||
PSU__USE__M_AXI_GP2 |
0,1 |
1 |
||||
PSU__MAXIGP2__DATA_WIDTH |
128,64,32 |
128 |
||||
PSU__USE__S_AXI_ACP |
0,1 |
0 |
||||
PSU__USE__S_AXI_GP0 |
0,1 |
0 |
||||
PSU__USE_DIFF_RW_CLK_GP0 |
0,1 |
0 |
||||
PSU__SAXIGP0__DATA_WIDTH |
128,64,32 |
128 |
||||
PSU__USE__S_AXI_GP1 |
0,1 |
0 |
||||
PSU__USE_DIFF_RW_CLK_GP1 |
0,1 |
0 |
||||
PSU__SAXIGP1__DATA_WIDTH |
128,64,32 |
128 |
||||
PS PL Interface related Parameters (continued) |
PSU__USE__S_AXI_GP2 |
0,1 |
0 |
|||
PSU__USE_DIFF_RW_CLK_GP2 |
0,1 |
0 |
||||
PSU__SAXIGP2__DATA_WIDTH |
128,64,32 |
128 |
||||
PSU__USE__S_AXI_GP3 |
0,1 |
0 |
||||
PSU__USE_DIFF_RW_CLK_GP3 |
0,1 |
0 |
||||
PSU__SAXIGP3__DATA_WIDTH |
128,64,32 |
128 |
||||
PSU__USE__S_AXI_GP4 |
0,1 |
0 |
||||
PSU__USE_DIFF_RW_CLK_GP4 |
0,1 |
0 |
||||
PSU__SAXIGP4__DATA_WIDTH |
128,64,32 |
128 |
||||
PSU__USE__S_AXI_GP5 |
0,1 |
0 |
||||
PSU__USE_DIFF_RW_CLK_GP5 |
0,1 |
0 |
||||
PSU__SAXIGP5__DATA_WIDTH |
128,64,32 |
128 |
||||
PSU__USE__S_AXI_GP6 |
0,1 |
0 |
||||
PSU__USE_DIFF_RW_CLK_GP6 |
0,1 |
0 |
||||
PSU__SAXIGP6__DATA_WIDTH |
128,64,32 |
128 |
||||
PSU__USE__S_AXI_ACE |
0,1 |
0 |
||||
PSU__USE__FABRIC__RST |
0,1 |
1 |
||||
|
PSU__USB__RESET__MODE |
Boot Pin, Shared MIO pin, Separate MIO pin, Disable |
Boot pin |
|
||
|
PSU__USB__RESET__POLARITY |
Active Low, Active High |
Active Low |
|
||
|
PSU__USB0__RESET__ENABLE |
0,1 |
0 |
|
||
|
PSU__USB0__RESET__IO |
<Select>,MIO 0 ..77 |
<select> |
|
||
|
PSU__USB1__RESET__ENABLE |
0,1 |
0 |
|
||
|
PSU__USB1__RESET__IO |
<Select>,MIO 0 .. 77 |
<select> |
|||
MIO Pin Properties like pull down, drive strength, direction and slew |
PSU_MIO_0_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
|||
PSU_MIO_0_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_0_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_0_SLEW |
fast,slow |
slow |
||||
PSU_MIO_0_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_1_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_1_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_1_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_1_SLEW |
fast,slow |
slow |
||||
PSU_MIO_1_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_2_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_2_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_2_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_2_SLEW |
fast,slow |
slow |
||||
PSU_MIO_2_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
MIO Pin Properties like pull down, drive strength, direction and slew (continued) |
PSU_MIO_3_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
|||
PSU_MIO_3_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_3_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_3_SLEW |
fast,slow |
slow |
||||
PSU_MIO_3_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_4_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_4_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_4_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_4_SLEW |
fast,slow |
slow |
||||
PSU_MIO_4_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_5_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_5_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_5_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_5_SLEW |
fast,slow |
slow |
||||
PSU_MIO_5_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_6_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_6_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_6_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_6_SLEW |
fast,slow |
slow |
||||
PSU_MIO_6_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_7_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_7_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_7_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_7_SLEW |
fast,slow |
slow |
||||
PSU_MIO_7_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_8_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_8_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_8_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_8_SLEW |
fast,slow |
slow |
||||
PSU_MIO_8_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_9_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_9_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_9_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_9_SLEW |
fast,slow |
slow |
||||
MIO Pin Properties like pull down, drive strength, direction and slew (continued) |
PSU_MIO_9_DIRECTION |
<Select>,in,out,inout |
<Select> |
|||
PSU_MIO_10_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_10_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_10_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_10_SLEW |
fast,slow |
slow |
||||
PSU_MIO_10_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_11_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_11_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_11_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_11_SLEW |
fast,slow |
slow |
||||
PSU_MIO_11_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_12_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_12_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_12_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_12_SLEW |
fast,slow |
slow |
||||
PSU_MIO_12_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_13_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_13_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_13_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_13_SLEW |
fast,slow |
slow |
||||
PSU_MIO_13_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_14_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_14_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_14_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_14_SLEW |
fast,slow |
slow |
||||
PSU_MIO_14_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_15_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_15_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_15_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_15_SLEW |
fast,slow |
slow |
||||
PSU_MIO_15_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_16_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_16_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_16_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
MIO Pin Properties like pull down, drive strength, direction and slew (continued) |
PSU_MIO_16_SLEW |
fast,slow |
slow |
|||
PSU_MIO_16_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_17_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_17_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_17_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_17_SLEW |
fast,slow |
slow |
||||
PSU_MIO_17_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_18_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_18_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_18_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_18_SLEW |
fast,slow |
slow |
||||
PSU_MIO_18_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_19_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_19_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_19_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_19_SLEW |
fast,slow |
slow |
||||
PSU_MIO_19_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_20_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_20_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_20_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_20_SLEW |
fast,slow |
slow |
||||
PSU_MIO_20_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_21_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_21_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_21_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_21_SLEW |
fast,slow |
slow |
||||
PSU_MIO_21_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_22_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_22_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_22_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_22_SLEW |
fast,slow |
slow |
||||
PSU_MIO_22_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_23_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_23_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
MIO Pin Properties like pull down, drive strength, direction and slew (continued) |
PSU_MIO_23_INPUT_TYPE |
cmos,schmitt |
schmitt |
|||
PSU_MIO_23_SLEW |
fast,slow |
slow |
||||
PSU_MIO_23_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_24_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_24_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_24_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_24_SLEW |
fast,slow |
slow |
||||
PSU_MIO_24_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_25_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_25_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_25_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_25_SLEW |
fast,slow |
slow |
||||
PSU_MIO_25_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_26_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_26_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_26_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_26_SLEW |
fast,slow |
slow |
||||
PSU_MIO_26_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_27_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_27_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_27_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_27_SLEW |
fast,slow |
slow |
||||
PSU_MIO_27_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_28_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_28_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_28_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_28_SLEW |
fast,slow |
slow |
||||
PSU_MIO_28_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_29_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_29_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_29_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_29_SLEW |
fast,slow |
slow |
||||
PSU_MIO_29_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_30_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
MIO Pin Properties like pull down, drive strength, direction and slew (continued) |
PSU_MIO_30_DRIVE_STRENGTH |
2,4,8,12 |
12 |
|||
PSU_MIO_30_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_30_SLEW |
fast,slow |
slow |
||||
PSU_MIO_30_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_31_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_31_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_31_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_31_SLEW |
fast,slow |
slow |
||||
PSU_MIO_31_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_32_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_32_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_32_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_32_SLEW |
fast,slow |
slow |
||||
PSU_MIO_32_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_33_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_33_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_33_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_33_SLEW |
fast,slow |
slow |
||||
PSU_MIO_33_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_34_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_34_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_34_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_34_SLEW |
fast,slow |
slow |
||||
PSU_MIO_34_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_35_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_35_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_35_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_35_SLEW |
fast,slow |
slow |
||||
PSU_MIO_35_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_36_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_36_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_36_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_36_SLEW |
fast,slow |
slow |
||||
PSU_MIO_36_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
MIO Pin Properties like pull down, drive strength, direction and slew (continued) |
PSU_MIO_37_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
|||
PSU_MIO_37_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_37_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_37_SLEW |
fast,slow |
slow |
||||
PSU_MIO_37_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_38_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_38_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_38_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_38_SLEW |
fast,slow |
slow |
||||
PSU_MIO_38_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_39_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_39_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_39_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_39_SLEW |
fast,slow |
slow |
||||
PSU_MIO_39_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_40_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_40_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_40_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_40_SLEW |
fast,slow |
slow |
||||
PSU_MIO_40_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_41_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_41_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_41_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_41_SLEW |
fast,slow |
slow |
||||
PSU_MIO_41_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_42_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_42_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_42_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_42_SLEW |
fast,slow |
slow |
||||
PSU_MIO_42_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_43_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_43_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_43_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_43_SLEW |
fast,slow |
slow |
||||
MIO Pin Properties like pull down, drive strength, direction and slew (continued) |
PSU_MIO_43_DIRECTION |
<Select>,in,out,inout |
<Select> |
|||
PSU_MIO_44_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_44_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_44_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_44_SLEW |
fast,slow |
slow |
||||
PSU_MIO_44_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_45_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_45_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_45_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_45_SLEW |
fast,slow |
slow |
||||
PSU_MIO_45_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_46_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_46_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_46_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_46_SLEW |
fast,slow |
slow |
||||
PSU_MIO_46_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_47_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_47_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_47_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_47_SLEW |
fast,slow |
slow |
||||
PSU_MIO_47_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_48_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_48_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_48_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_48_SLEW |
fast,slow |
slow |
||||
PSU_MIO_48_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_49_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_49_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_49_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_49_SLEW |
fast,slow |
slow |
||||
PSU_MIO_49_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_50_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_50_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_50_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
MIO Pin Properties like pull down, drive strength, direction and slew (continued) |
PSU_MIO_50_SLEW |
fast,slow |
slow |
|||
PSU_MIO_50_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_51_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_51_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_51_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_51_SLEW |
fast,slow |
slow |
||||
PSU_MIO_51_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_52_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_52_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_52_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_52_SLEW |
fast,slow |
slow |
||||
PSU_MIO_52_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_53_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_53_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_53_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_53_SLEW |
fast,slow |
slow |
||||
PSU_MIO_53_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_54_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_54_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_54_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_54_SLEW |
fast,slow |
slow |
||||
PSU_MIO_54_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_55_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_55_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_55_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_55_SLEW |
fast,slow |
slow |
||||
PSU_MIO_55_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_56_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_56_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_56_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_56_SLEW |
fast,slow |
slow |
||||
PSU_MIO_56_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_57_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_57_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
MIO Pin Properties like pull down, drive strength, direction and slew (continued) |
PSU_MIO_57_INPUT_TYPE |
cmos,schmitt |
schmitt |
|||
PSU_MIO_57_SLEW |
fast,slow |
slow |
||||
PSU_MIO_57_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_58_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_58_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_58_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_58_SLEW |
fast,slow |
slow |
||||
PSU_MIO_58_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_59_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_59_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_59_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_59_SLEW |
fast,slow |
slow |
||||
PSU_MIO_59_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_60_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_60_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_60_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_60_SLEW |
fast,slow |
slow |
||||
PSU_MIO_60_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_61_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_61_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_61_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_61_SLEW |
fast,slow |
slow |
||||
PSU_MIO_61_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_62_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_62_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_62_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_62_SLEW |
fast,slow |
slow |
||||
PSU_MIO_62_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_63_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_63_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_63_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_63_SLEW |
fast,slow |
slow |
||||
PSU_MIO_63_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_64_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
MIO Pin Properties like pull down, drive strength, direction and slew (continued) |
PSU_MIO_64_DRIVE_STRENGTH |
2,4,8,12 |
12 |
|||
PSU_MIO_64_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_64_SLEW |
fast,slow |
slow |
||||
PSU_MIO_64_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_65_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_65_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_65_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_65_SLEW |
fast,slow |
slow |
||||
PSU_MIO_65_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_66_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_66_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_66_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_66_SLEW |
fast,slow |
slow |
||||
PSU_MIO_66_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_67_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_67_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_67_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_67_SLEW |
fast,slow |
slow |
||||
PSU_MIO_67_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_68_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_68_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_68_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_68_SLEW |
fast,slow |
slow |
||||
PSU_MIO_68_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_69_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_69_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_69_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_69_SLEW |
fast,slow |
slow |
||||
PSU_MIO_69_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_70_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_70_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_70_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_70_SLEW |
fast,slow |
slow |
||||
PSU_MIO_70_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
MIO Pin Properties like pull down, drive strength, direction and slew (continued) |
PSU_MIO_71_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
|||
PSU_MIO_71_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_71_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_71_SLEW |
fast,slow |
slow |
||||
PSU_MIO_71_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_72_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_72_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_72_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_72_SLEW |
fast,slow |
slow |
||||
PSU_MIO_72_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_73_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_73_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_73_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_73_SLEW |
fast,slow |
slow |
||||
PSU_MIO_73_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_74_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_74_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_74_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_74_SLEW |
fast,slow |
slow |
||||
PSU_MIO_74_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_75_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_75_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_75_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_75_SLEW |
fast,slow |
slow |
||||
PSU_MIO_75_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_76_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_76_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_76_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_76_SLEW |
fast,slow |
slow |
||||
PSU_MIO_76_DIRECTION |
<Select>,in,out,inout |
<Select> |
||||
PSU_MIO_77_PULLUPDOWN |
pulldown,pullup,disable |
pullup |
||||
PSU_MIO_77_DRIVE_STRENGTH |
2,4,8,12 |
12 |
||||
PSU_MIO_77_INPUT_TYPE |
cmos,schmitt |
schmitt |
||||
PSU_MIO_77_SLEW |
fast,slow |
slow |
||||
|
PSU_MIO_77_DIRECTION |
<Select>,in,out,inout |
<Select> |
|||
Bank 0 Standard |
PSU_BANK_0_IO_STANDARD |
LVCMOS18,LVCMOS25,LVCMOS33 |
LVCMOS33 |
|||
Bank 1 Standard |
PSU_BANK_1_IO_STANDARD |
LVCMOS18,LVCMOS25,LVCMOS33 |
LVCMOS33 |
|||
Bank 2 Standard |
PSU_BANK_2_IO_STANDARD |
LVCMOS18,LVCMOS25,LVCMOS33 |
LVCMOS33 |
|||
Bank 2 Standard |
PSU_BANK_3_IO_STANDARD |
|
LVCMOS18,LVCMOS25,LVCMOS33 |
|
LVCMOS33 |
|
Clocking related Parameters and Divisors |
PSU__CRF_APB__APLL_CTRL__FRACDATA |
|
0 |
|||
PSU__CRF_APB__VPLL_CTRL__FRACDATA |
|
0 |
||||
PSU__CRF_APB__DPLL_CTRL__FRACDATA |
|
0 |
||||
PSU__CRL_APB__IOPLL_CTRL__
|
|
0 |
||||
PSU__CRL_APB__RPLL_CTRL__FRACDATA |
|
0 |
||||
PSU__CRF_APB__DPLL_CTRL__DIV2 |
0,1 |
1 |
||||
PSU__CRF_APB__APLL_CTRL__DIV2 |
0,1 |
1 |
||||
PSU__CRF_APB__VPLL_CTRL__DIV2 |
0,1 |
1 |
||||
PSU__CRL_APB__IOPLL_CTRL__DIV2 |
0,1 |
1 |
||||
PSU__CRL_APB__RPLL_CTRL__DIV2 |
0,1 |
1 |
||||
PSU__CRF_APB__APLL_CTRL__FBDIV |
|
72 |
||||
PSU__CRF_APB__DPLL_CTRL__FBDIV |
|
60 |
||||
PSU__CRF_APB__VPLL_CTRL__FBDIV |
|
90 |
||||
PSU__CRF_APB__APLL_TO_LPD_CTRL__
|
|
3 |
||||
PSU__CRF_APB__DPLL_TO_LPD_CTRL__
|
|
2 |
||||
PSU__CRF_APB__VPLL_TO_LPD_CTRL__
|
|
3 |
||||
PSU__CRF_APB__ACPU_CTRL__DIVISOR0 |
|
1 |
||||
PSU__CRF_APB__DBG_TRACE_CTRL__
|
|
2 |
||||
Display Port |
PSU__DISPLAYPORT__PERIPHERAL__
|
0,1 |
0 |
|||
PSU__DISPLAYPORT__LANE0__ENABLE |
0,1 |
0 |
||||
PSU__DISPLAYPORT__LANE0__IO |
<Select>,GT Lane1,GT Lane3 |
<Select> |
||||
PSU__DISPLAYPORT__LANE1__ENABLE |
0,1 |
0 |
||||
PSU__DISPLAYPORT__LANE1__IO |
<Select>,GT Lane0,GT Lane2 |
<Select> |
||||
Clocking related Parameters and Divisors |
PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 |
|
2 |
|||
PSU__CRF_APB__APM_CTRL__DIVISOR0 |
|
1 |
||||
PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 |
|
5 |
||||
PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 |
|
1 |
||||
PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 |
|
64 |
||||
PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 |
|
1 |
||||
PSU__CRF_APB__DP_STC_REF_CTRL__
|
|
6 |
||||
PSU__CRF_APB__DP_STC_REF_CTRL__
|
|
10 |
||||
PSU__CRF_APB__DDR_CTRL__DIVISOR0 |
|
3 |
||||
PSU__CRF_APB__GPU_REF_CTRL__
|
|
2 |
||||
PSU__CRF_APB__AFI0_REF_CTRL__
|
|
2 |
||||
PSU__CRF_APB__AFI0_REF__ENABLE |
0,1 |
0 |
||||
PSU__CRF_APB__AFI1_REF_CTRL__
|
|
2 |
||||
PSU__CRF_APB__AFI1_REF__ENABLE |
0,1 |
0 |
||||
PSU__CRF_APB__AFI2_REF_CTRL__
|
|
2 |
||||
PSU__CRF_APB__AFI2_REF__ENABLE |
0,1 |
0 |
||||
PSU__CRF_APB__AFI3_REF_CTRL__
|
|
2 |
||||
PSU__CRF_APB__AFI3_REF__ENABLE |
0,1 |
0 |
||||
PSU__CRF_APB__AFI4_REF_CTRL__
|
|
2 |
||||
PSU__CRF_APB__AFI4_REF__ENABLE |
0,1 |
0 |
||||
PSU__CRF_APB__AFI5_REF_CTRL__
|
|
2 |
||||
PSU__CRF_APB__AFI5_REF__ENABLE |
0,1 |
0 |
||||
PSU__CRF_APB__SATA_REF_CTRL__
|
|
5 |
||||
SATA Related Parameters |
PSU__SATA__PERIPHERAL__ENABLE |
0,1 |
0 |
|||
PSU__SATA__LANE0__ENABLE |
0,1 |
0 |
||||
PSU__SATA__LANE0__IO |
<Select>,GT Lane0,GT Lane2 |
<Select> |
||||
PSU__SATA__LANE1__ENABLE |
0,1 |
0 |
||||
PSU__SATA__LANE1__IO |
<Select>,GT Lane1,GT Lane3 |
<Select> |
||||
Clocking related Parameters and Divisors |
PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 |
|
6 |
|||
PSU__CRL_APB__PL0_REF_CTRL__
|
|
15 |
||||
PSU__CRL_APB__PL1_REF_CTRL__
|
|
4 |
||||
PSU__CRL_APB__PL2_REF_CTRL__
|
|
4 |
||||
PSU__CRL_APB__PL3_REF_CTRL__
|
|
4 |
||||
PSU__CRL_APB__PL0_REF_CTRL__
|
|
1 |
||||
PSU__CRL_APB__PL1_REF_CTRL__
|
|
1 |
||||
PSU__CRL_APB__PL2_REF_CTRL__
|
|
1 |
||||
PSU__CRL_APB__PL3_REF_CTRL__
|
|
1 |
||||
PSU__CRL_APB__AMS_REF_CTRL__
|
|
30 |
||||
PSU__CRL_APB__AMS_REF_CTRL__
|
|
1 |
||||
PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 |
|
15 |
||||
PSU__CRL_APB__AFI6_REF_CTRL__
|
|
3 |
||||
PSU__CRL_APB__AFI6__ENABLE |
0,1 |
0 |
||||
PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 |
|
5 |
||||
PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 |
|
15 |
||||
PSU__CRL_APB__USB3__ENABLE |
0,1 |
0 |
||||
PSU__CRF_APB__GDMA_REF_CTRL__
|
|
2 |
||||
Clocking related Parameters and Divisors (continued) |
PSU__CRF_APB__DPDMA_REF_CTRL__
|
|
2 |
|||
PSU__CRF_APB__TOPSW_MAIN_CTRL__
|
|
2 |
||||
PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 |
|
5 |
||||
PSU__CRF_APB__GTGREF0_REF_CTRL__
|
|
-1 |
||||
PSU__CRF_APB__GTGREF0__ENABLE |
NA |
NA |
||||
PSU__CRF_APB__DBG_TSTMP_CTRL__
|
|
2 |
||||
PSU__CRL_APB__IOPLL_CTRL__FBDIV |
|
90 |
||||
PSU__CRL_APB__RPLL_CTRL__FBDIV |
|
90 |
||||
PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 |
|
3 |
||||
PSU__CRL_APB__RPLL_TO_FPD_CTRL__
|
|
3 |
||||
PSU__CRL_APB__GEM0_REF_CTRL__
|
|
12 |
||||
PSU__CRL_APB__GEM1_REF_CTRL__
|
|
12 |
||||
PSU__CRL_APB__GEM2_REF_CTRL__
|
|
12 |
||||
PSU__CRL_APB__GEM3_REF_CTRL__
|
|
12 |
||||
PSU__CRL_APB__GEM0_REF_CTRL__
|
|
1 |
||||
PSU__CRL_APB__GEM1_REF_CTRL__
|
|
1 |
||||
PSU__CRL_APB__GEM2_REF_CTRL__
|
|
1 |
||||
PSU__CRL_APB__GEM3_REF_CTRL__
|
|
1 |
||||
PSU__CRL_APB__GEM_TSU_REF_CTRL__
|
|
4 |
||||
PSU__CRL_APB__GEM_TSU_REF_CTRL__
|
|
1 |
||||
PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 |
|
6 |
||||
Clocking related Parameters and Divisors (continued)
|
PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 |
|
1 |
|||
PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 |
|
6 |
||||
PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 |
|
1 |
||||
PSU__CRL_APB__QSPI_REF_CTRL__
|
|
5 |
||||
PSU__CRL_APB__QSPI_REF_CTRL__
|
|
1 |
||||
PSU__CRL_APB__SDIO0_REF_CTRL__
|
|
7 |
||||
PSU__CRL_APB__SDIO0_REF_CTRL__
|
|
1 |
||||
PSU__CRL_APB__SDIO1_REF_CTRL__
|
|
7 |
||||
PSU__CRL_APB__SDIO1_REF_CTRL__
|
|
1 |
||||
PSU__CRL_APB__UART0_REF_CTRL__
|
|
15 |
||||
PSU__CRL_APB__UART0_REF_CTRL__
|
|
1 |
||||
PSU__CRL_APB__UART1_REF_CTRL__
|
|
15 |
||||
PSU__CRL_APB__UART1_REF_CTRL__
|
|
1 |
||||
PSU__CRL_APB__I2C0_REF_CTRL__
|
|
15 |
||||
PSU__CRL_APB__I2C0_REF_CTRL__
|
|
1 |
||||
PSU__CRL_APB__I2C1_REF_CTRL__
|
|
15 |
||||
PSU__CRL_APB__I2C1_REF_CTRL__
|
|
1 |
||||
PSU__CRL_APB__SPI0_REF_CTRL__
|
|
7 |
||||
PSU__CRL_APB__SPI0_REF_CTRL__
|
|
1 |
||||
PSU__CRL_APB__SPI1_REF_CTRL__
|
|
7 |
||||
Clocking related Parameters and Divisors (continued)
|
PSU__CRL_APB__SPI1_REF_CTRL__
|
|
1 |
|||
PSU__CRL_APB__CAN0_REF_CTRL__
|
|
15 |
||||
PSU__CRL_APB__CAN0_REF_CTRL__
|
|
1 |
||||
PSU__CRL_APB__CAN1_REF_CTRL__
|
|
15 |
||||
PSU__CRL_APB__CAN1_REF_CTRL__
|
|
1 |
||||
PSU__CRL_APB__DEBUG_R5_ATCLK_
|
|
6 |
||||
PSU__CRL_APB__CPU_R5_CTRL__
|
|
3 |
||||
PSU__CRL_APB__OCM_MAIN_CTRL__
|
|
3 |
||||
PSU__CRL_APB__IOU_SWITCH_CTRL__
|
|
6 |
||||
PSU__CRL_APB__CSU_PLL_CTRL__
|
|
3 |
||||
PSU__CRL_APB__PCAP_CTRL__DIVISOR0 |
|
6 |
||||
PSU__CRL_APB__LPD_LSBUS_CTRL__
|
|
15 |
||||
PSU__CRL_APB__LPD_SWITCH_CTRL__
|
|
3 |
||||
PSU__CRL_APB__DBG_LPD_CTRL__
|
|
6 |
||||
PSU__CRL_APB__NAND_REF_CTRL__
|
|
15 |
||||
PSU__CRL_APB__NAND_REF_CTRL__
|
|
1 |
||||
PSU__CRL_APB__ADMA_REF_CTRL__
|
|
3 |
||||
PSU__CRF_APB__APLL_CTRL__SRCSEL |
PSS_REF_CLK |
PSS_REF_CLK |
||||
PSU__CRF_APB__DPLL_CTRL__SRCSEL |
PSS_REF_CLK |
PSS_REF_CLK |
||||
PSU__CRF_APB__VPLL_CTRL__SRCSEL |
PSS_REF_CLK |
PSS_REF_CLK |
||||
PSU__CRF_APB__ACPU_CTRL__SRCSEL |
APLL,DPLL,VPLL |
APLL |
||||
Clocking related Parameters and Divisors (continued)
|
PSU__CRF_APB__DBG_TRACE_CTRL__
|
IOPLL,DPLL,APLL |
IOPLL |
|||
PSU__CRF_APB__DBG_FPD_CTRL__
|
IOPLL,DPLL,APLL |
IOPLL |
||||
PSU__CRF_APB__APM_CTRL__SRCSEL |
<Select> |
<Select> |
||||
PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL |
VPLL,DPLL,RPLL |
VPLL |
||||
PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL |
VPLL,DPLL,RPLL |
VPLL |
||||
PSU__CRF_APB__DP_STC_REF_CTRL__
|
VPLL,DPLL,RPLL,
|
VPLL |
||||
PSU__CRF_APB__DDR_CTRL__SRCSEL |
DPLL,VPLL |
DPLL |
||||
PSU__CRF_APB__GPU_REF_CTRL__
|
IOPLL,VPLL,DPLL |
DPLL |
||||
PSU__CRF_APB__AFI0_REF_CTRL__
|
APLL,VPLL,DPLL |
DPLL |
||||
PSU__CRF_APB__AFI1_REF_CTRL__
|
APLL,VPLL,DPLL |
DPLL |
||||
PSU__CRF_APB__AFI2_REF_CTRL__
|
APLL,VPLL,DPLL |
DPLL |
||||
PSU__CRF_APB__AFI3_REF_CTRL__
|
APLL,VPLL,DPLL |
DPLL |
||||
PSU__CRF_APB__AFI4_REF_CTRL__
|
APLL,VPLL,DPLL |
DPLL |
||||
PSU__CRF_APB__AFI5_REF_CTRL__
|
APLL,VPLL,DPLL |
DPLL |
||||
PSU__CRF_APB__SATA_REF_CTRL__
|
APLL,IOPLL,DPLL |
IOPLL |
||||
PSU__CRF_APB__PCIE_REF_CTRL__
|
IOPLL,RPLL,DPLL |
IOPLL |
||||
PSU__CRL_APB__PL0_REF_CTRL__SRCSEL |
DPLL,IOPLL,RPLL |
RPLL |
||||
PSU__CRL_APB__PL1_REF_CTRL__SRCSEL |
DPLL,IOPLL,RPLL |
RPLL |
||||
PSU__CRL_APB__PL2_REF_CTRL__SRCSEL |
DPLL,IOPLL,RPLL |
RPLL |
||||
PSU__CRL_APB__PL3_REF_CTRL__SRCSEL |
DPLL,IOPLL,RPLL |
RPLL |
||||
PSU__CRF_APB__GDMA_REF_CTRL__
|
APLL,VPLL,DPLL |
APLL |
||||
PSU__CRF_APB__DPDMA_REF_CTRL__
|
APLL,VPLL,DPLL |
APLL |
||||
PSU__CRF_APB__TOPSW_MAIN_CTRL__
|
APLL,VPLL,DPLL |
DPLL |
||||
Clocking related Parameters and Divisors (continued)
|
PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL |
APLL,IOPLL,DPLL |
IOPLL |
|||
PSU__CRF_APB__GTGREF0_REF_CTRL__
|
NA |
NA |
||||
PSU__CRF_APB__DBG_TSTMP_CTRL__
|
APLL,DPLL,IOPLL |
IOPLL |
||||
PSU__CRL_APB__IOPLL_CTRL__SRCSEL |
PSS_REF_CLK |
PSS_REF_CLK |
||||
PSU__CRL_APB__RPLL_CTRL__SRCSEL |
PSS_REF_CLK |
PSS_REF_CLK |
||||
PSU__CRL_APB__GEM0_REF_CTRL__
|
DPLL,IOPLL,RPLL |
IOPLL |
||||
PSU__CRL_APB__GEM1_REF_CTRL__
|
DPLL,IOPLL,RPLL |
IOPLL |
||||
PSU__CRL_APB__GEM2_REF_CTRL__
|
DPLL,IOPLL,RPLL |
IOPLL |
||||
PSU__CRL_APB__GEM3_REF_CTRL__
|
DPLL,IOPLL,RPLL |
IOPLL |
||||
PSU__CRL_APB__GEM_TSU_REF_CTRL__
|
IOPLL,RPLL,DPLL |
RPLL |
||||
PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL |
DPLL,IOPLL,RPLL |
IOPLL |
||||
PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL |
DPLL,IOPLL,RPLL |
IOPLL |
||||
PSU__CRL_APB__QSPI_REF_CTRL__
|
DPLL,IOPLL,RPLL |
IOPLL |
||||
PSU__CRL_APB__SDIO0_REF_CTRL__
|
VPLL,IOPLL,RPLL |
RPLL |
||||
PSU__CRL_APB__SDIO1_REF_CTRL__
|
VPLL,IOPLL,RPLL |
RPLL |
||||
PSU__CRL_APB__UART0_REF_CTRL__
|
DPLL,IOPLL,RPLL |
IOPLL |
||||
PSU__CRL_APB__UART1_REF_CTRL__
|
DPLL,IOPLL,RPLL |
IOPLL |
||||
PSU__CRL_APB__I2C0_REF_CTRL__
|
DPLL,IOPLL,RPLL |
IOPLL |
||||
PSU__CRL_APB__I2C1_REF_CTRL__
|
DPLL,IOPLL,RPLL |
IOPLL |
||||
PSU__CRL_APB__SPI0_REF_CTRL__
|
DPLL,IOPLL,RPLL |
RPLL |
||||
Clocking related Parameters and Divisors (continued)
|
PSU__CRL_APB__SPI1_REF_CTRL__
|
DPLL,IOPLL,RPLL |
RPLL |
|||
PSU__CRL_APB__CAN0_REF_CTRL__
|
DPLL,IOPLL,RPLL |
IOPLL |
||||
PSU__CRL_APB__CAN1_REF_CTRL__
|
DPLL,IOPLL,RPLL |
IOPLL |
||||
PSU__CRL_APB__DEBUG_R5_ATCLK_
|
RPLL,IOPLL,DPLL |
RPLL |
||||
PSU__CRL_APB__CPU_R5_CTRL__SRCSEL |
IOPLL,RPLL,DPLL |
RPLL |
||||
PSU__CRL_APB__OCM_MAIN_CTRL__
|
IOPLL,RPLL,DPLL |
IOPLL |
||||
PSU__CRL_APB__IOU_SWITCH_CTRL__
|
IOPLL,RPLL,DPLL |
RPLL |
||||
PSU__CRL_APB__CSU_PLL_CTRL__
|
DPLL,IOPLL,RPLL,SysOsc |
SysOsc |
||||
PSU__CRL_APB__PCAP_CTRL__SRCSEL |
DPLL,IOPLL,RPLL |
RPLL |
||||
PSU__CRL_APB__LPD_LSBUS_CTRL__
|
IOPLL,RPLL,DPLL |
IOPLL |
||||
PSU__CRL_APB__LPD_SWITCH_CTRL__
|
IOPLL,RPLL,DPLL |
IOPLL |
||||
PSU__CRL_APB__DBG_LPD_CTRL__
|
IOPLL,RPLL,DPLL |
IOPLL |
||||
PSU__CRL_APB__NAND_REF_CTRL__
|
DPLL,IOPLL,RPLL |
IOPLL |
||||
PSU__CRL_APB__ADMA_REF_CTRL__
|
RPLL,IOPLL,DPLL |
IOPLL |
||||
PSU__CRL_APB__DLL_REF_CTRL__
|
IOPLL,RPLL |
IOPLL |
||||
PSU__CRL_APB__AMS_REF_CTRL__
|
IOPLL,RPLL,DPLL |
IOPLL |
||||
PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL |
RPLL,IOPLL,DPLL |
IOPLL |
||||
PSU__CRL_APB__AFI6_REF_CTRL__
|
RPLL,IOPLL,DPLL |
IOPLL |
||||
PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL |
IOPLL,RPLL,DPLL |
IOPLL |
||||
PSU__IOU_SLCR__WDT_CLK_SEL__
|
APB,External |
APB |
||||
PSU__FPD_SLCR__WDT_CLK_SEL__
|
APB,External |
APB |
||||
Clocking related Parameters and Divisors (continued)
|
PSU__IOU_SLCR__IOU_TTC_APB_CLK__
|
APB,CPU_R5,PSS_REF_CLK |
APB |
|||
PSU__IOU_SLCR__IOU_TTC_APB_CLK__
|
APB,CPU_R5,PSS_REF_CLK |
APB |
||||
PSU__IOU_SLCR__IOU_TTC_APB_CLK__
|
APB,CPU_R5,PSS_REF_CLK |
APB |
||||
PSU__IOU_SLCR__IOU_TTC_APB_CLK__
|
APB,CPU_R5,PSS_REF_CLK |
APB |
||||
PSU__CRF_APB__APLL_FRAC_CFG__
|
0,1 |
0 |
||||
PSU__CRF_APB__VPLL_FRAC_CFG__
|
0,1 |
0 |
||||
PSU__CRF_APB__DPLL_FRAC_CFG__
|
0,1 |
0 |
||||
PSU__CRL_APB__IOPLL_FRAC_CFG__
|
0,1 |
0 |
||||
PSU__CRL_APB__RPLL_FRAC_CFG__
|
0,1 |
0 |
||||
PSU__OVERRIDE__BASIC_CLOCK |
0,1 |
0 |
||||
PSU__PL_CLK0_BUF |
FALSE,TRUE |
TRUE |
||||
PSU__PL_CLK1_BUF |
FALSE,TRUE |
FALSE |
||||
PSU__PL_CLK2_BUF |
FALSE,TRUE |
FALSE |
||||
PSU__PL_CLK3_BUF |
FALSE,TRUE |
FALSE |
||||
PSU__CRF_APB__APLL_CTRL__FRACFREQ |
|
27.138 |
||||
PSU__CRF_APB__VPLL_CTRL__FRACFREQ |
|
27.138 |
||||
PSU__CRF_APB__DPLL_CTRL__FRACFREQ |
|
27.138 |
||||
PSU__CRL_APB__IOPLL_CTRL__
|
|
27.138 |
||||
PSU__CRL_APB__RPLL_CTRL__FRACFREQ |
|
27.138 |
||||
PSU__IOU_SLCR__TTC0__ACT_FREQMHZ |
0.000000,600.000000 |
100 |
||||
PSU__IOU_SLCR__TTC1__ACT_FREQMHZ |
0.000000,600.000000 |
100 |
||||
PSU__IOU_SLCR__TTC2__ACT_FREQMHZ |
0.000000,600.000000 |
100 |
||||
PSU__IOU_SLCR__TTC3__ACT_FREQMHZ |
600.000000,0.000000 |
100 |
||||
PSU__IOU_SLCR__WDT0__ACT_
|
0.000000,100.000000 |
100 |
||||
PSU__FPD_SLCR__WDT1__ACT_
|
|
100 |
||||
Clocking related Parameters and Divisors (continued)
|
PSU__CRF_APB__ACPU_CTRL__ACT_
|
|
1199.988 |
|||
PSU__CRF_APB__DBG_TRACE_CTRL__
|
|
249.997 |
||||
PSU__CRF_APB__DBG_FPD_CTRL__ACT_
|
|
249.997 |
||||
PSU__CRF_APB__APM_CTRL__ACT_
|
|
1 |
||||
PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ |
|
320 |
||||
PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ |
|
25 |
||||
PSU__CRF_APB__DP_STC_REF_CTRL__
|
|
27 |
||||
PSU__CRF_APB__DDR_CTRL__ACT_
|
|
374.996 |
||||
PSU__DDR__INTERFACE__FREQMHZ |
0.000000,600.000000 |
400.00 |
||||
PSU__CRF_APB__GPU_REF_CTRL__ACT_
|
|
499.995 |
||||
PSU__CRF_APB__AFI0_REF_CTRL__ACT_
|
|
667 |
||||
PSU__CRF_APB__AFI1_REF_CTRL__ACT_
|
|
667 |
||||
PSU__CRF_APB__AFI2_REF_CTRL__ACT_
|
|
667 |
||||
PSU__CRF_APB__AFI3_REF_CTRL__ACT_
|
|
667 |
||||
PSU__CRF_APB__AFI4_REF_CTRL__ACT_
|
|
667 |
||||
PSU__CRF_APB__AFI5_REF_CTRL__ACT_
|
|
667 |
||||
PSU__CRF_APB__SATA_REF_CTRL__ACT_
|
|
250 |
||||
PSU__CRF_APB__PCIE_REF_CTRL__ACT_
|
|
250 |
||||
PSU__CRL_APB__PL0_REF_CTRL__ACT_
|
|
99.999 |
||||
PSU__CRL_APB__PL1_REF_CTRL__ACT_
|
|
100 |
||||
PSU__CRL_APB__PL2_REF_CTRL__ACT_
|
|
100 |
||||
Clocking related Parameters and Divisors (continued)
|
PSU__CRL_APB__PL3_REF_CTRL__ACT_
|
|
100 |
|||
PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ |
|
599.994 |
||||
PSU__CRF_APB__DPDMA_REF_CTRL__
|
|
599.994 |
||||
PSU__CRF_APB__TOPSW_MAIN_CTRL__
|
|
499.995 |
||||
PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ |
|
99.999 |
||||
PSU__CRF_APB__GTGREF0_REF_CTRL__
|
|
-1 |
||||
PSU__CRF_APB__DBG_TSTMP_CTRL__
|
|
249.997 |
||||
PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ |
|
125 |
||||
PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ |
|
125 |
||||
PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ |
|
125 |
||||
PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ |
|
125 |
||||
PSU__CRL_APB__GEM_TSU_REF_CTRL__
|
|
250 |
||||
PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ |
|
250 |
||||
PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ |
|
250 |
||||
PSU__CRL_APB__QSPI_REF_CTRL__ACT_
|
|
300 |
||||
PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ |
|
200 |
||||
PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ |
|
200 |
||||
PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ |
|
100 |
||||
PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ |
|
100 |
||||
PSU__CRL_APB__I2C0_REF_CTRL__ACT_
|
|
100 |
||||
Clocking related Parameters and Divisors (continued)
|
PSU__CRL_APB__I2C1_REF_CTRL__ACT_
|
|
100 |
|||
PSU__CRL_APB__SPI0_REF_CTRL__ACT_
|
|
214 |
||||
PSU__CRL_APB__SPI1_REF_CTRL__ACT_
|
|
214 |
||||
PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ |
|
100 |
||||
PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ |
|
100 |
||||
PSU__CRL_APB__DEBUG_R5_ATCLK_
|
|
1000 |
||||
PSU__CRL_APB__CPU_R5_CTRL__ACT_
|
|
499.995 |
||||
PSU__CRL_APB__OCM_MAIN_CTRL__
|
|
500 |
||||
PSU__CRL_APB__IOU_SWITCH_CTRL__
|
|
249.997 |
||||
PSU__CRL_APB__CSU_PLL_CTRL__ACT_
|
|
180 |
||||
PSU__CRL_APB__PCAP_CTRL__ACT_
|
|
249.997 |
||||
PSU__CRL_APB__LPD_LSBUS_CTRL__
|
|
99.999 |
||||
PSU__CRL_APB__LPD_SWITCH_CTRL__
|
|
499.995 |
||||
PSU__CRL_APB__DBG_LPD_CTRL__ACT_
|
|
249.997 |
||||
PSU__CRL_APB__NAND_REF_CTRL__
|
|
100 |
||||
PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ |
|
499.995 |
||||
PSU__CRL_APB__DLL_REF_CTRL__ACT_
|
|
1500 |
||||
PSU__CRL_APB__AMS_REF_CTRL__ACT_
|
|
50 |
||||
PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ |
|
99.999 |
||||
PSU__CRL_APB__AFI6_REF_CTRL__ACT_
|
|
500 |
||||
Clocking related Parameters and Divisors (continued)
|
PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ |
|
20 |
|||
PSU__CRF_APB__ACPU_CTRL__
|
0.000000,1500.000000 |
1200 |
||||
PSU__CRF_APB__DBG_TRACE_CTRL__
|
0.000000,125.000000 |
125 |
||||
PSU__CRF_APB__DBG_FPD_CTRL__
|
0.000000,250.000000 |
250 |
||||
PSU__CRF_APB__APM_CTRL__FREQMHZ |
-2,-1 |
1 |
||||
PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ |
0.000000,320.000000 |
320 |
||||
PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ |
0.000000,25.000000 |
25 |
||||
PSU__CRF_APB__DP_STC_REF_CTRL__
|
0.000000,27.000000 |
27 |
||||
PSU__CRF_APB__DDR_CTRL__FREQMHZ |
100.000000,667.000000 |
800 |
||||
PSU__CRF_APB__GPU_REF_CTRL__
|
0.000000,667.000000 |
500 |
||||
PSU__CRF_APB__AFI0_REF_CTRL__
|
0.000000,667.000000 |
667 |
||||
PSU__CRF_APB__AFI1_REF_CTRL__
|
0.000000,667.000000 |
667 |
||||
PSU__CRF_APB__AFI2_REF_CTRL__
|
0.000000,667.000000 |
667 |
||||
PSU__CRF_APB__AFI3_REF_CTRL__
|
0.000000,667.000000 |
667 |
||||
PSU__CRF_APB__AFI4_REF_CTRL__
|
0.000000,667.000000 |
667 |
||||
PSU__CRF_APB__AFI5_REF_CTRL__
|
0.000000,667.000000 |
667 |
||||
PSU__CRF_APB__SATA_REF_CTRL__
|
0.000000,250.000000 |
250 |
||||
PSU__CRF_APB__PCIE_REF_CTRL__
|
0.000000,250.000000 |
250 |
||||
PSU__CRL_APB__PL0_REF_CTRL__
|
0.000000,400.000000 |
100 |
||||
PSU__CRL_APB__PL1_REF_CTRL__
|
0.000000,400.000000 |
100 |
||||
PSU__CRL_APB__PL2_REF_CTRL__
|
0.000000,400.000000 |
100 |
||||
Clocking related Parameters and Divisors (continued)
|
PSU__CRL_APB__PL3_REF_CTRL__
|
0.000000,400.000000 |
100 |
|||
PSU__CRF_APB__GDMA_REF_CTRL__
|
0.000000,667.000000 |
600 |
||||
PSU__CRF_APB__DPDMA_REF_CTRL__
|
0.000000,667.000000 |
600 |
||||
PSU__CRF_APB__TOPSW_MAIN_CTRL__
|
0.000000,600.000000 |
533.33 |
||||
PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ |
0.000000,100.000000 |
100 |
||||
PSU__CRF_APB__GTGREF0_REF_CTRL__
|
-2,-1 |
-1 |
||||
PSU__CRF_APB__DBG_TSTMP_CTRL__
|
0.000000,250.000000 |
250 |
||||
PSU__CRL_APB__GEM0_REF_CTRL__
|
0.000000,125.000000 |
125 |
||||
PSU__CRL_APB__GEM1_REF_CTRL__
|
0.000000,125.000000 |
125 |
||||
PSU__CRL_APB__GEM2_REF_CTRL__
|
0.000000,125.000000 |
125 |
||||
PSU__CRL_APB__GEM3_REF_CTRL__
|
0.000000,125.000000 |
125 |
||||
PSU__CRL_APB__GEM_TSU_REF_CTRL__
|
0.000000,250.000000 |
250 |
||||
PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ |
0.000000,250.000000 |
250 |
||||
PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ |
0.000000,250.000000 |
250 |
||||
PSU__CRL_APB__QSPI_REF_CTRL__
|
0.000000,300.000000 |
300 |
||||
PSU__CRL_APB__SDIO0_REF_CTRL__
|
0.000000,200.000000 |
200 |
||||
PSU__CRL_APB__SDIO1_REF_CTRL__
|
0.000000,200.000000 |
200 |
||||
PSU__CRL_APB__UART0_REF_CTRL__
|
0.000000,100.000000 |
100 |
||||
PSU__CRL_APB__UART1_REF_CTRL__
|
0.000000,100.000000 |
100 |
||||
PSU__CRL_APB__I2C0_REF_CTRL__
|
0.000000,100.000000 |
100 |
||||
Clocking related Parameters and Divisors (continued)
|
PSU__CRL_APB__I2C1_REF_CTRL__
|
0.000000,100.000000 |
100 |
|||
PSU__CRL_APB__SPI0_REF_CTRL__
|
0.000000,200.000000 |
200 |
||||
PSU__CRL_APB__SPI1_REF_CTRL__
|
0.000000,200.000000 |
200 |
||||
PSU__CRL_APB__CAN0_REF_CTRL__
|
0.000000,100.000000 |
100 |
||||
PSU__CRL_APB__CAN1_REF_CTRL__
|
0.000000,100.000000 |
100 |
||||
PSU__CRL_APB__DEBUG_R5_ATCLK_
|
0.000000,1000.000000 |
1000 |
||||
PSU__CRL_APB__CPU_R5_CTRL__
|
0.000000,500.000000 |
500 |
||||
PSU__CRL_APB__OCM_MAIN_CTRL__
|
0.000000,600.000000 |
500 |
||||
PSU__CRL_APB__IOU_SWITCH_CTRL__
|
0.000000,267.000000 |
267 |
||||
PSU__CRL_APB__CSU_PLL_CTRL__
|
0.000000,400.000000 |
180 |
||||
PSU__CRL_APB__PCAP_CTRL__FREQMHZ |
0.000000,250.000000 |
250 |
||||
PSU__CRL_APB__LPD_LSBUS_CTRL__
|
0.000000,100.000000 |
100 |
||||
PSU__CRL_APB__LPD_SWITCH_CTRL__
|
0.000000,600.000000 |
500 |
||||
PSU__CRL_APB__DBG_LPD_CTRL__
|
0.000000,267.000000 |
250 |
||||
PSU__CRL_APB__NAND_REF_CTRL__
|
0.000000,100.000000 |
100 |
||||
PSU__CRL_APB__ADMA_REF_CTRL__
|
0.000000,600.000000 |
500 |
||||
PSU__CRL_APB__DLL_REF_CTRL__
|
0.000000,1500.000000 |
1500 |
||||
PSU__CRL_APB__AMS_REF_CTRL__
|
0.000000,52.000000 |
50 |
||||
PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ |
0.000000,100.000000 |
100 |
||||
PSU__CRL_APB__AFI6_REF_CTRL__
|
0.000000,600.000000 |
500 |
||||
PSU__CRL_APB__USB3_DUAL_REF_CTRL_FREQMHZ |
0.000000,20.000000 |
20 |
||||
Clocking related Parameters and Divisors (continued)
|
PSU__IOU_SLCR__TTC0__FREQMHZ |
0.000000,600.000000 |
100 |
|||
PSU__IOU_SLCR__TTC1__FREQMHZ |
0.000000,600.000000 |
100 |
||||
PSU__IOU_SLCR__TTC2__FREQMHZ |
0.000000,600.000000 |
100 |
||||
PSU__IOU_SLCR__TTC3__FREQMHZ |
0.000000,600.000000 |
100 |
||||
PSU__IOU_SLCR__WDT0__FREQMHZ |
0.000000,100.000000 |
100 |
||||
PSU__FPD_SLCR__WDT1__FREQMHZ |
0.000000,100.000000 |
100 |
||||
CSU Tamper Enable |
PSU__CSU__CSU_TAMPER_0__ENABLE |
0,1 |
0 |
|||
PSU__CSU__CSU_TAMPER_1__ENABLE |
0,1 |
0 |
||||
PSU__CSU__CSU_TAMPER_2__ENABLE |
0,1 |
0 |
||||
PSU__CSU__CSU_TAMPER_3__ENABLE |
0,1 |
0 |
||||
PSU__CSU__CSU_TAMPER_4__ENABLE |
0,1 |
0 |
||||
PSU__CSU__CSU_TAMPER_5__ENABLE |
0,1 |
0 |
||||
PSU__CSU__CSU_TAMPER_6__ENABLE |
0,1 |
0 |
||||
PSU__CSU__CSU_TAMPER_7__ENABLE |
0,1 |
0 |
||||
PSU__CSU__CSU_TAMPER_8__ENABLE |
0,1 |
0 |
||||
PSU__CSU__CSU_TAMPER_9__ENABLE |
0,1 |
0 |
||||
PSU__CSU__CSU_TAMPER_10__ENABLE |
0,1 |
0 |
||||
PSU__CSU__CSU_TAMPER_11__ENABLE |
0,1 |
0 |
||||
PSU__CSU__CSU_TAMPER_12__ENABLE |
0,1 |
0 |
||||
CSU Tamper Erase block RAM |
PSU__CSU__CSU_TAMPER_0__ERASE_
|
0,1 |
0 |
|||
PSU__CSU__CSU_TAMPER_1__ERASE_
|
0,1 |
0 |
||||
PSU__CSU__CSU_TAMPER_2__ERASE_
|
0,1 |
0 |
||||
PSU__CSU__CSU_TAMPER_3__ERASE_
|
0,1 |
0 |
||||
PSU__CSU__CSU_TAMPER_4__ERASE_
|
0,1 |
0 |
||||
PSU__CSU__CSU_TAMPER_5__ERASE_
|
0,1 |
0 |
||||
PSU__CSU__CSU_TAMPER_6__ERASE_
|
0,1 |
0 |
||||
PSU__CSU__CSU_TAMPER_7__ERASE_
|
0,1 |
0 |
||||
PSU__CSU__CSU_TAMPER_8__ERASE_
|
0,1 |
0 |
||||
CSU Tamper Erase block RAM (continued) |
PSU__CSU__CSU_TAMPER_9__ERASE_
|
0,1 |
0 |
|||
PSU__CSU__CSU_TAMPER_10__ERASE_
|
0,1 |
0 |
||||
PSU__CSU__CSU_TAMPER_11__ERASE_
|
0,1 |
0 |
||||
PSU__CSU__CSU_TAMPER_12__ERASE_
|
0,1 |
0 |
||||
CSU Tamper Response |
PSU__CSU__CSU_TAMPER_0__RESPONSE |
|
<Select>,SEC_LOCKDOWN_0,
|
<Select> |
||
PSU__CSU__CSU_TAMPER_1__RESPONSE |
|
<Select>,SEC_LOCKDOWN_0,
|
<Select> |
|||
PSU__CSU__CSU_TAMPER_2__RESPONSE |
|
<Select>,SEC_LOCKDOWN_0,
|
<Select> |
|||
PSU__CSU__CSU_TAMPER_3__RESPONSE |
|
<Select>,SEC_LOCKDOWN_0,
|
<Select> |
|||
PSU__CSU__CSU_TAMPER_4__RESPONSE |
|
<Select>,SEC_LOCKDOWN_0,
|
<Select> |
|||
PSU__CSU__CSU_TAMPER_5__RESPONSE |
|
<Select>,SEC_LOCKDOWN_0,
|
<Select> |
|||
PSU__CSU__CSU_TAMPER_6__RESPONSE |
|
<Select>,SEC_LOCKDOWN_0,
|
<Select> |
|||
PSU__CSU__CSU_TAMPER_7__RESPONSE |
|
<Select>,SEC_LOCKDOWN_0,
|
<Select> |
|||
CSU Tamper Response (continued) |
PSU__CSU__CSU_TAMPER_8__RESPONSE |
|
<Select>,SEC_LOCKDOWN_0,
|
<Select> |
||
PSU__CSU__CSU_TAMPER_9__RESPONSE |
<Select>,SEC_LOCKDOWN_0,
|
<Select> |
||||
PSU__CSU__CSU_TAMPER_10__
|
<Select>,SEC_LOCKDOWN_0,
|
<Select> |
||||
PSU__CSU__CSU_TAMPER_11__
|
<Select>,SEC_LOCKDOWN_0,
|
<Select> |
||||
PSU__CSU__CSU_TAMPER_12__
|
<Select>,SEC_LOCKDOWN_0,
|
<Select> |
||||
PSU__GEN_IPI_0__MASTER |
NONE,APU,RPU0,RPU1,
|
APU |
||||
PSU__GEN_IPI_1__MASTER |
NONE,APU,RPU0,RPU1,
|
RPU0 |
||||
PSU__GEN_IPI_2__MASTER |
NONE,APU,RPU0,RPU1,
|
RPU1 |
||||
PSU__GEN_IPI_3__MASTER |
NONE,PMU |
PMU |
||||
IPI Master |
PSU__GEN_IPI_4__MASTER |
NONE,PMU |
PMU |
|||
PSU__GEN_IPI_5__MASTER |
NONE,PMU |
PMU |
||||
PSU__GEN_IPI_6__MASTER |
NONE,PMU |
PMU |
||||
PSU__GEN_IPI_7__MASTER |
NONE,APU,RPU0,RPU1,
|
NONE |
||||
PSU__GEN_IPI_8__MASTER |
NONE,APU,RPU0,RPU1,
|
NONE |
||||
PSU__GEN_IPI_9__MASTER |
NONE,APU,RPU0,RPU1,
|
NONE |
||||
IPI Master (Continued) |
PSU__GEN_IPI_10__MASTER |
NONE,APU,RPU0,RPU1,
|
NONE |
|||
PSU__NUM_FABRIC_RESETS |
0,1,2,3,4 |
1 |
||||
PSU__GPIO_EMIO__WIDTH |
NA |
[94:0] |
||||
PSU__REPORT__DBGLOG |
0,1 |
0 |
||||
Notes:
1.
Reserve, Wireless controller, Satellite communication controller, Data acquisition and signal processing controllers,
2. ADMA is also referenced as LPD_DMA throughout this guide. These two terms are synonymous. 3. GDMA is also referenced as FPD_DMA throughout this guide. These two terms are synonymous. 4. PSU__PMU__EMIO_GPI__ENABLE and PSU__PMU__EMIO_GPO__ENABLE belongs to PMU processor local bank GPI3 and GPO3. While GPI3 and GPO3 are reserved for communication with the PL, GPI3 monitors the GPIs from the PL. GPO3 is dedicated to the GPOs to the PL. 5. PSU__PMU__GPI0__ENABLE to PSU__PMU__GPI5__ENABLE signals belong to PMU processor local bank GPI0 (only accessible by the PMU processor) and GPI0 is reserved for the dedicated PMU processor subsystem features. These are general purpose wakes from MIO. MIO[26] -> GPI1[10], MIO[27] -> GPI1[11] ... MIO[31] -> GPI1[15]. 6. PSU__PMU__GPO0__ENABLE to PSU__PMU__GPO5__ENABLE signals belong to PMU processor local bank GPO1 (only accessible by the PMU processor) and GPO1 is reserved for the dedicated PMU processor subsystem features. GPO1 is dedicated to the GPOs assigned to the MIO for signaling and power-supply management (GPOs to MIO). Use the following guidelines to signal the powering up of power rails: GPO1[0] = 1: Signal to turn on a basic digital switch for the FET for VCC_PSINTFP . GPO1[1] = 1: Signal to turn on the FET for VCCINT . SDWT1 is also referred as FPD SWDT or FPD_SWDT as this is in FPD domain. SDWT0 is also referred as LPD SWDT or LPD_SWDT as this is in LPD domain. 7. The PSU__NUM_FABRIC_RESETS parameter will enable the PL fabric reset signals (pl_resetn{0:3}) as described in Fabric Reset Enable . 8. The default values of Clocking parameters (FBDIV, SRCSEL, DIVISOR0, DIVISOR1, etc.) mentioned in this table are part specific and depending on the speed grades. You need to open PCW and cross check for the corresponding values for these parameters based on their requirements. |
|