SD Configuration - SD Configuration - 3.4 English - PG201

Zynq UltraScale+ MPSoC Processing System Product Guide (PG201)
Document_ID
PG201
Release_Date
2022-05-11
Version
3.4 English

When configuring the SD 0 or SD 1 controller there are multiple options for the SD Slot Type.

Figure 4-6: Configuring SD Controller Options in I/O Configuration

X-Ref Target - Figure 4-6

Configuring_SD_Controller.png

• Slot Type

° SD 2.0 : Set controller to operate in SD 2.0 mode.

° SD 3.0 : Set controller to operate in SD 3.0 mode.

° SD 3.0 AutoDir : Set controller to operate in SD 3.0 mode with support for nxp-level shifters.

° eMMC : Set controller to operate in eMMC mode.

• Data Transfer Mode : Set the data mode for the SD controller.

• OTAP Delay : Select the output tap delay values for various SD modes. For more information, see DLL Clock Mode for SD section in Zynq UltraScale All Programmable MPSoC Technical Reference Manual (UG1085) [Ref 1] .

• ITAP Delay : Select the input tap delay values for various SD modes. For more information, see DLL Clock Mode for SD section in Zynq UltraScale All Programmable MPSoC Technical Reference Manual (UG1085) [Ref 1] .

• CD : Enable the SD Card Detect Signal (only available in SD mode).

• Power : Enable GRP Power.

• WP : Enable write protect signals (only available in SD mode).