Resets - 3.4 English

Zynq UltraScale+ MPSoC Processing System Product Guide (PG201)

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3.4 English

There are many applicable resets:

External power on reset (POR) - Triggered by external pin assertion.

Internal POR - Triggered by software register write or safety errors.

"System" reset - Triggered by external pin assertion, or register write or safety errors. This reset does not reset debug logic.

PS "System" reset - Triggered by a hardware error or by a register write. This is a PS only reset and PL remains active.

PS POR reset - Similar to External POR but only for PS.

Full power subsystem (FPS) reset - Triggered by error or register write and used to reset Full Power Domain.

RPU Reset - Triggered by errors or register write, explicitly to reset RPU.

See Fabric Reset Enable . Also for more details about the individual resets, see the Zynq UltraScale All Programmable MPSoC Technical Reference Manual (UG1085) [Ref 1] .