The interrupts from the processing system I/O peripherals (IOP) are routed to the PL and assert asynchronously to the fclk clocks.
The PL can asynchronously assert up to 20 interrupts to the PS.
• 16 interrupt signals are mapped to the interrupt controller as a peripheral interrupt where each interrupt signal is set to a priority level and mapped to one or both of the CPUs. To use more that one interrupt signal, use a Concat block in the Vivado IP integrator to automatically size the width of the interrupt vector.
• The remaining four PL interrupt signals are inverted and routed to the nFIQ and nIRQ interrupt directly to the signals to the private peripheral interrupt (PPI) unit of the interrupt controller. There is an nFIQ and nIRQ interrupt for each of two CPUs.
The PS to PL, and PL to PS interrupts are listed in
Table: Interrupt Map for PS Configuration Wizard (PCW)
. For details on the interrupt signals, see the Interrupts chapter in the
Zynq UltraScale All Programmable MPSoC Technical Reference Manual
(UG1085)
[Ref 1]
.
See
PS-PL Configuration
for Vivado Design Suite implementation.
S.No |
Interrupt ID |
Interrupt Name |
Description |
Type |
---|---|---|---|---|
PL-PS Interrupts (Interrupts that go from PL to PS) |
||||
1 |
121-128, 136-143 (See Table: Pin mapping to Interrupt IDs for Pin mapping to each interrupt ID) |
IRQ-F2P[15:0] |
Shared Interrupts from PL logic to GICs of real-time processing unit (RPU) or application processing unit (APU) |
Shared Interrupts |
2 |
31 |
A53-Core_0 nIRQ |
Cortex™ A53 Core0 Private Peripheral Legacy IRQ Interrupt |
Private Peripheral Interrupt |
3 |
31 |
A53-Core_1 nIRQ |
Cortex A53 Core1 Private Peripheral Legacy IRQ Interrupt |
Private Peripheral Interrupt |
4 |
31 |
A53-Core_2 nIRQ |
Cortex A53 Core2 Private Peripheral Legacy IRQ Interrupt |
Private Peripheral Interrupt |
5 |
31 |
A53-Core_3 nIRQ |
Cortex A53 Core3 Private Peripheral Legacy IRQ Interrupt |
Private Peripheral Interrupt |
6 |
28 |
A53-Core_0 nFIQ |
Cortex A53 Core0 Private Peripheral Legacy FIQ Interrupt |
Private Peripheral Interrupt |
7 |
28 |
A53-Core_1 nFIQ |
Cortex A53 Core1 Private Peripheral Legacy FIQ Interrupt |
Private Peripheral Interrupt |
8 |
28 |
A53-Core_2 nFIQ |
Cortex A53 Core2 Private Peripheral Legacy FIQ Interrupt |
Private Peripheral Interrupt |
9 |
28 |
A53-Core_3 nFIQ |
Cortex A53 Core3 Private Peripheral Legacy FIQ Interrupt |
Private Peripheral Interrupt |
PS -PL Interrupts (Interrupts coming from PS to PL) |
||||
1 |
1 |
IRQ_P2F_RPU Performance Monitor 0 |
RPU Performance Monitor 0 Interrupt |
Shared Interrupt |
2 |
1 |
IRQ_P2F_RPU Performance Monitor 1 |
RPU Performance Monitor 1 Interrupt |
Shared Interrupt |
3 |
1 |
IRQ_P2F_OCM Error |
On-chip RAM (OCM) Error Interrupt |
Shared Interrupt |
4 |
1 |
IRQ_P2F_LPD APB Interrupts |
OR of all AMBA peripheral bus (APB) interrupts from LPD. Refer to the technical reference manual for APB Interrupt and Register Information. |
Shared Interrupt |
5 |
1 |
IRQ_P2F_R5 Core0_ECC _Error |
RPU CPU0 error-correction code (ECC) errors interrupt. All ECC interrupts of CPU0 are combined into this interrupt. |
Shared Interrupt |
6 |
1 |
IRQ_P2F_R5 Core1_ECC_Error |
RPU CPU1 ECC errors interrupt. All ECC interrupts of CPU1 are combined into this interrupt. |
Shared Interrupt |
7 |
1 |
IRQ_P2F_NAND |
NAND/NOR/SRAM Static Memory Controller Interrupt |
Shared Interrupt |
8 |
1 |
IRQ_P2F_QSPI |
SPI flash memory interrupt |
Shared Interrupt |
9 |
1 |
IRQ_P2F_GPIO |
GPIO interrupt |
Shared Interrupt |
10 |
1 |
IRQ_P2F_I2C0 |
I2C0 interrupt |
Shared Interrupt |
11 |
1 |
IRQ_P2F_I2C1 |
I2C1 interrupt |
Shared Interrupt |
12 |
1 |
IRQ_P2F_SPI0 |
SPI0 interrupt |
Shared Interrupt |
13 |
1 |
IRQ_P2F_SPI1 |
SPI1 interrupt |
Shared Interrupt |
14 |
1 |
IRQ_P2F_UART0 |
UART0 interrupt |
Shared Interrupt |
15 |
1 |
IRQ_P2F_UART1 |
UART1 interrupt |
Shared Interrupt |
16 |
1 |
IRQ_P2F_CAN0 |
CAN0 interrupt |
Shared Interrupt |
17 |
1 |
IRQ_P2F_CAN1 |
CAN1 interrupt |
Shared Interrupt |
18 |
1 |
IRQ_P2F_LPD_APM |
Or of all LPD AXI performance monitors (APMs) |
Shared Interrupt |
19 |
1 |
IRQ_P2F_RTC_ALARM |
RTC Alarm Interrupt |
Shared Interrupt |
20 |
1 |
IRQ_P2F_RTC_SECONDS |
RTC Seconds Interrupt |
Shared Interrupt |
21 |
1 |
IRQ_P2F_CLKMON |
Clock monitor coming from CRL |
Shared Interrupt |
22 |
1 |
S_PL_IRQ_IPI_CHANNEL0 |
OR' of all of inter-processor interrupt (IPIs) targeted to IPI channel 0 |
Shared Interrupt |
23 |
1 |
S_PL_IRQ_IPI_CHANNEL1 |
OR' of all of inter-processor interrupt (IPIs) targeted to IPI channel 1 |
Shared Interrupt |
24 |
1 |
S_PL_IRQ_IPI_CHANNEL2 |
OR' of all of inter-processor interrupt (IPIs) targeted to IPI channel 2 |
Shared Interrupt |
25 |
1 |
S_PL_IRQ_IPI_CHANNEL7 |
OR' of all of inter-processor interrupt (IPIs) targeted to IPI channel 7 |
Shared Interrupt |
26 |
1 |
S_PL_IRQ_IPI_CHANNEL8 |
OR' of all of inter-processor interrupt (IPIs) targeted to IPI channel 8 |
Shared Interrupt |
27 |
1 |
S_PL_IRQ_IPI_CHANNEL9 |
OR' of all of inter-processor interrupt (IPIs) targeted to IPI channel 9 |
Shared Interrupt |
28 |
1 |
S_PL_IRQ_IPI_CHANNEL10 |
OR' of all of inter-processor interrupt (IPIs) targeted to IPI channel 10 |
Shared Interrupt |
29 |
1 |
IRQ_P2F_TTC0_0 |
Triple Timer 0 Counter 0 Interrupt |
Shared Interrupt |
30 |
1 |
IRQ_P2F_TTC0_1 |
Triple Timer 0 Counter 1 Interrupt |
Shared Interrupt |
31 |
1 |
IRQ_P2F_TTC0_2 |
Triple Timer 0 Counter 2 Interrupt |
Shared Interrupt |
32 |
1 |
IRQ_P2F_TTC1_0 |
Triple Timer 1 Counter 0 Interrupt |
Shared Interrupt |
33 |
1 |
IRQ_P2F_TTC1_1 |
Triple Timer 1 Counter 1 Interrupt |
Shared Interrupt |
34 |
1 |
IRQ_P2F_TTC1_2 |
Triple Timer 1 Counter 2 Interrupt |
Shared Interrupt |
35 |
1 |
IRQ_P2F_TTC2_0 |
Triple Timer 2 Counter 0 Interrupt |
Shared Interrupt |
36 |
1 |
IRQ_P2F_TTC2_1 |
Triple Timer 2 Counter 1 Interrupt |
Shared Interrupt |
37 |
1 |
IRQ_P2F_TTC2_2 |
Triple Timer 2 Counter 2 Interrupt |
Shared Interrupt |
38 |
1 |
IRQ_P2F_TTC3_0 |
Triple Timer 3 Counter 0 Interrupt |
Shared Interrupt |
39 |
1 |
IRQ_P2F_TTC3_1 |
Triple Timer 3 Counter 1 Interrupt |
Shared Interrupt |
40 |
1 |
IRQ_P2F_TTC3_2 |
Triple Timer 3 Counter 2 Interrupt |
Shared Interrupt |
41 |
1 |
IRQ_P2F_SDIO0 |
SDIO0 interrupt |
Shared Interrupt |
42 |
1 |
IRQ_P2F_SDIO1 |
SDIO1 interrupt |
Shared Interrupt |
43 |
1 |
IRQ_P2F_SDIO0_wake |
SDIO0 wake interrupt |
Shared Interrupt |
44 |
1 |
IRQ_P2F_SDIO1_wake |
SDIO1 wake interrupt |
Shared Interrupt |
45 |
1 |
IRQ_P2F_LP_WDT |
Watchdog timer (WDT) in the LPD (IOU) (IOU is Input Output Unit) |
Shared Interrupt |
46 |
1 |
IRQ_P2F_CSUPMU_WDT |
WDT in the Configuration Security Unit Performance monitoring unit (CSUPMU) |
Shared Interrupt |
47 |
1 |
IRQ_P2F_ATB Err LPD |
AMBA trace bus (ATB) interrupt |
Shared Interrupt |
48 |
1 |
IRQ_P2F_AIB_AXI |
AXI Isolation Block (AIB) AXI interrupt |
Shared Interrupt |
49 |
1 |
IRQ_P2F_AMS |
Analog mixed-signal unit (AMS) interrupt |
Shared Interrupt |
50 |
1 |
IRQ_P2F_GigabitEth0 |
Ethernet0 interrupt |
Shared Interrupt |
51 |
1 |
IRQ_P2F_GigabitEth_
|
Ethernet0 wake-up interrupt |
Shared Interrupt |
52 |
1 |
IRQ_P2F_GigabitEth1 |
Gigabit Ethernet1 interrupt |
Shared Interrupt |
53 |
1 |
IRQ_P2F_GigabitEth_
|
Gigabit Ethernet1 wake-up interrupt |
Shared Interrupt |
54 |
1 |
IRQ_P2F_GigabitEth2 |
Gigabit Ethernet2 interrupt |
Shared Interrupt |
55 |
1 |
IRQ_P2F_GigabitEth2_
|
Gigabit Ethernet2 wake-up interrupt |
Shared Interrupt |
56 |
1 |
IRQ_P2F_GigabitEth3 |
Gigabit Ethernet3 interrupt |
Shared Interrupt |
57 |
1 |
IRQ_P2F_GigabitEth3_
|
Gigabit Ethernet3 wake-up interrupt |
Shared Interrupt |
58 |
4 |
IRQ_P2F_USB3_0_Endpoint |
USB3_0 Endpoint related interrupts. Four Interrupts Enabled. One interrupt each for Bulk, Isochronous, Interrupt and Control type. |
Shared Interrupt |
59 |
1 |
IRQ_P2F_USB3_0_OTG |
USB3_0 OTG interrupt |
Shared Interrupt |
60 |
4 |
IRQ_P2F_USB3_1_Endpoint |
USB3_1 Endpoint related interrupts. Four Interrupts Enabled. One interrupt each for Bulk, Isochronous, Interrupt and Control type. |
Shared Interrupt |
61 |
1 |
IRQ_P2F_USB3_1_OTG |
USB3_1 OTG interrupt |
Shared Interrupt |
62 |
1 |
IRQ_P2F_USB3_0_1 PMU_WAKEUP |
Bit 0 is wake up from USB3_0 to power monitoring unit (PMU) while bit 1 is wake up from USB3_1 to PMU |
Shared Interrupt |
63 |
1 |
IRQ_P2F_ADMA (1) _Chan_0 |
LPD_DMA(ADMA) channel 0 interrupt |
Shared Interrupt |
64 |
1 |
IRQ_P2F_ADMA (1) _Chan_1 |
LPD_DMA(ADMA) channel 1 interrupt |
Shared Interrupt |
65 |
1 |
IRQ_P2F_ADMA (1) _Chan_2 |
LPD_DMA(ADMA) channel 2 interrupt |
Shared Interrupt |
66 |
1 |
IRQ_P2F_ADMA (1) _Chan_3 |
LPD_DMA(ADMA) channel 3 interrupt |
Shared Interrupt |
67 |
1 |
IRQ_P2F_ADMA (1) _Chan_4 |
LPD_DMA(ADMA) channel 4 interrupt |
Shared Interrupt |
68 |
1 |
IRQ_P2F_ADMA (1) _Chan_5 |
LPD_DMA(ADMA) channel 5 interrupt |
Shared Interrupt |
69 |
1 |
IRQ_P2F_ADMA (1) _Chan_6 |
LPD_DMA(ADMA) channel 6 interrupt |
Shared Interrupt |
70 |
1 |
IRQ_P2F_ADMA (1) _Chan_7 |
LPD_DMA(ADMA) channel 7 interrupt |
Shared Interrupt |
71 |
1 |
IRQ_P2F_CSU |
Device Configuration Module Interrupt |
Shared Interrupt |
72 |
1 |
IRQ_P2F_CSU_DMA |
DMA for Configuration and Security Unit (CSU) interrupt |
Shared Interrupt |
73 |
1 |
IRQ_P2F_EFUSE |
EFUSE interrupt |
Shared Interrupt |
74 |
1 |
IRQ_P2F_XMPU_LPD |
Xilinx memory protection unit (XMPU) error Interrupt for OCM and LPD peripherals |
Shared Interrupt |
75 |
1 |
IRQ_P2F_DDR_SS |
DDR controller subsystem interrupt |
Shared Interrupt |
76 |
1 |
IRQ_P2F_FP_WDT |
Top Level Watch Dog Timer Interrupt. |
Shared Interrupt |
77 |
1 |
IRQ_P2F_PCIE_MSI |
PCIE_MSI[0]=PCIe interrupt for MSI vectors 31 to 0 PCIE_MSI[1]=PCIe interrupt for MSI vectors 63 to 32 |
Shared Interrupt |
78 |
1 |
IRQ_P2F_PCIE_Legacy |
PCIE legacy (INTA/BC/D) interrupts |
Shared Interrupt |
79 |
1 |
IRQ_P2F_PCIE_DMA |
PCIE Bridge DMA interrupts |
Shared Interrupt |
80 |
1 |
IRQ_P2F_PCIE_MSC |
PCIE misc (error etc) interrupts |
Shared Interrupt |
81 |
1 |
IRQ_P2F_DPORT |
Display port general purpose interrupt |
Shared Interrupt |
82 |
1 |
IRQ_P2F_FPD_APB_INT |
OR'd of all APB interrupts from LPD |
Shared Interrupt |
83 |
1 |
IRQ_P2F_FPD ATB Error |
ATB interrupt for FPD |
Shared Interrupt |
84 |
1 |
IRQ_P2F_DPDMA interrupt |
DPDMA interrupt |
Shared Interrupt |
85 |
1 |
IRQ_P2F_APM FPD |
Or of all APMs for FPD |
Shared Interrupt |
86 |
1 |
IRQ_P2F_GDMA (2) _Chan_0 |
Interrupt from general purpose (FPD_DMA(GDMA)) Channel 0 |
Shared Interrupt |
87 |
1 |
IRQ_P2F_GDMA (2) _Chan_1 |
Interrupt from FPD_DMA(GDMA) Channel 1 |
Shared Interrupt |
88 |
1 |
IRQ_P2F_GDMA (2) _Chan_2 |
Interrupt from FPD_DMA(GDMA) Channel 2 |
Shared Interrupt |
89 |
1 |
IRQ_P2F_GDMA (2) _Chan_3 |
Interrupt from FPD_DMA(GDMA) Channel 3 |
Shared Interrupt |
90 |
1 |
IRQ_P2F_GDMA (2) _Chan_4 |
Interrupt from FPD_DMA(GDMA) Channel 4 |
Shared Interrupt |
91 |
1 |
IRQ_P2F_GDMA (2) _Chan_5 |
Interrupt from FPD_DMA(GDMA) Channel 5 |
Shared Interrupt |
92 |
1 |
IRQ_P2F_GDMA (2) _Chan_6 |
Interrupt from FPD_DMA(GDMA) Channel 6 |
Shared Interrupt |
93 |
1 |
IRQ_P2F_GDMA (2) _Chan_7 |
Interrupt from FPD_DMA(GDMA) Channel 7 |
Shared Interrupt |
94 |
1 |
IRQ_P2F_GPU |
All of GPU interrupts are OR-ed together |
Shared Interrupt |
95 |
1 |
IRQ_P2F_SATA |
SATA controller interrupt |
Shared Interrupt |
96 |
1 |
IRQ_P2F_XMPU FPD |
Xilinx memory protection unit (XMPU) error Interrupt for DDR and FPD peripherals |
Shared Interrupt |
97 |
4 |
IRQ_P2F_APU_CPUMNT |
VCPUMT |
Shared Interrupt |
98 |
4 |
IRQ_P2F_APU_CTI |
Cross trigger interface (CTI) |
Shared Interrupt |
99 |
4 |
IRQ_P2F_APU_PMU |
Performance Monitor Unit Interrupt |
Shared Interrupt |
100 |
4 |
IRQ_P2F_APU_COMM |
APU Communication Error |
Shared Interrupt |
101 |
1 |
IRQ_P2F_APU_L2ERR |
L2 Cache |
Shared Interrupt |
102 |
1 |
IRQ_P2F_APU_EXTERR |
EXTERR |
Shared Interrupt |
103 |
1 |
IRQ_P2F_APU_REGS |
REGISTER Interrupt |
Shared Interrupt |
104 |
1 |
IRQ_P2F_INTF_PPD_CCI |
Cache coherent interconnect (CCI) Interrupt from FPD |
Shared Interrupt |
105 |
1 |
IRQ_P2F_INTF_FPD_SMMU |
System Memory Management Unit (SMMU) Interrupt from FPD |
Shared Interrupt |
Notes: 1. ADMA is also referenced as LPD_DMA throughout this guide. These two terms are synonymous. 2. GDMA is also referenced as FPD_DMA throughout this guide. These two terms are synonymous. |
The Processing System IP core employs logic to handle PL interrupts, the number which varies from 1 to 16 depending on your selection. The number of interrupts connected to IRQ_F2P are calculated and the logic ensures the correct order of an interrupt assignment.
The Processing System IP interrupts from IOPs are available to custom master interfaces in PL.