Peripheral - 3.4 English

Zynq UltraScale+ MPSoC Processing System Product Guide (PG201)

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3.4 English

Low Speed

Memory Interface. These are the static memory controllers present in the PS.

Note: The Vivado Integrated Design Environment (IDE) shows that SD 3.0 supports 8 bit data mode. However, it supports only 4 bit data mode, the remaining 4 bits are used for control signals. The Vivado IDE is aligned with the register database.

I/O Peripherals. These are the I/O peripherals present in the PS.

Application Processing Unit. These are APU specific resources such as watch dog timer, Trace and Triple Timer Counter.