PLL Options for Output Clocks - 3.4 English

Zynq UltraScale+ MPSoC Processing System Product Guide (PG201)

Document ID
Release Date
3.4 English

There are five PLLs available in the MPSoC that are spread across the two domains, LPD and FPD. There are three PLLs namely APLL, DPLL and VPLL in the FPD domain while the RPLL and the IOPLL are in the LPD domain. PCW provides an option to make use of the cross domain PLLs to be used to source the cross-over peripheral. This gives additional options to select from a pool of all PLLs.

Figure 4-9: PLL Options for Output Clocks

X-Ref Target - Figure 4-9