PL Clocks - 3.4 English

Zynq UltraScale+ MPSoC Processing System Product Guide (PG201)

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3.4 English

The Processing System IP provides four clocks to the PL. Processing System IP enables configuration of these clocks to be used in the PL. Processing System IP inserts a BUFG for each of the PL clocks through parameters similar to C_FCLK_CLK0_BUF. Programmable Logic clocks are configured for 99.99 MHz by default.