PCIe Configuration - 3.4 English

Zynq UltraScale+ MPSoC Processing System Product Guide (PG201)

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3.4 English
Figure 4-17: PCIe Configuration

X-Ref Target - Figure 4-17


See the UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156) [Ref 9] for a description of the properties.

Note: Deadlock situations can occur when the PS PCIe shares path between the CCI and the FPD Main Switch with an external master targeting the PS PCIe interface. Avoid using PL DMA unit on S_AXI_HPC[0:1]_FPD, S_AXI_LPD, or on any other masters to exercise PCIe traffic because the shared path between the CCI and core switch can result in deadlock situations. For more information, see PCI Express Controller Chapter of the Zynq UltraScale All Programmable MPSoC Technical Reference Manual (UG1085) [Ref 1] .