Output Generation - 3.4 English

Zynq UltraScale+ MPSoC Processing System Product Guide (PG201)

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3.4 English

For details about common core output files, see “Generating IP Output Products” in the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 4] .

The Vivado design tool exports the Hardware Platform Specification for your design to the Software Development Kit (SDK). The following four files are exported to SDK:

The system.hdf file opens by default when SDK launches. The address map of your system read from this file is shown by default in the SDK window.

The psu_init.tcl , psu_init.c and psu_init.h files contain the initialization code for the Zynq UltraScale+ MPSoC processing system and initialization settings for DDR, clocks, plls, and MIOs. SDK uses these settings when initializing the processing system so that applications can be run on top of the processing system.

° psu_init.tcl : This Zynq UltraScale+ MPSoC Processor System initialization with the Tcl file is used for the device initialization Xilinx® System Debugger (XSDB) flow.

° psu_init.c: Generated by the PS Configuration Wizard (PCW), this header file for the first stage boot loader (FSBL) contains proc of a psu_init() and the return values. The FSBL uses only this file, and it calls the psu_init() functions, and checks return values.

° psu_init.h: Generated by the PCW, this file implements the psu_init() . This file also contains some testing code. This testing code enhances the testing performed by the PCW.

The supporting .c and .h files (described earlier) are also produced by the PCW.