Output Clocks - 3.4 English

Zynq UltraScale+ MPSoC Processing System Product Guide (PG201)

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3.4 English

In the default mode (when Enable Manual Mode is turned off), the wizard (PCW) automatically calculates the M (Multiplier) and D (Divisor) values to ensure that the tool meets the requested frequency to the nearest possible value. The wizard might or might not achieve all the requested values since each PLL caters to multiple peripherals. An internal algorithm creates the best possible solution based on the following conditions:

When Ethernet is enabled, wizard tries to give the precedence to the solution which has the Ethernet frequency of 125 MHz.

When Ethernet is enabled and if there are multiple clocking solutions with the identical Ethernet frequency of 125 MHz, then the tool will take the precedence of the solution that will have the least possible total error (sum of requested frequencies-sum of actual frequencies) value of various peripherals.

The tool will also take the precedence of the solution with least possible total error value of various peripherals even when the Ethernet is disabled.

Figure 4-8: Clock Configuration Page (Output Clocks)

X-Ref Target - Figure 4-8


Enable Manual Mode – When you select this mode, different options are displayed. You can directly input the M and D values for various PLLs as well as individual divisor values enabling finer control. For more details, see Output Clocks (Enable Manual Mode) .

Note: When you switch between manual and auto modes, clock settings in the manual mode are lost and default clock settings are shown in the auto mode.