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Zynq UltraScale+ MPSoC Processing System Product Guide (PG201)

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3.4 English

Memory Address Map (Bank-Row-Col mapping) – Indicates the mapping between the AXI address bus and the physical memory.

Data mask and DBI – Usage of data mask (DM) and data bus inversion (DBI).

DIMM Address mirror – Compensates for swapped address bits on the odd rank for clamshell PCB topologies.

Parity - Enables DDR4 parity checking

Power Down Enable - Power down after a PWRTMG.powerdown_to_x32 cycles

Clock Stop - Stop the clock to DRAM during self-refresh or during power down.

Low-Power Auto Self-Refresh - Controls self-refresh temperature ranges or enable automatic mode

Temp Controlled Refresh - Allows the refresh rate to be adjusted by temperature

Temp Controlled Refresh Range - Temperature range for determining refresh rate

Fine Granularity Refresh Mode - Generates more frequent refreshes with shorter tRFC times

Self Refresh Abort - Enables the self refresh abort bit in the DRAM MR4 register

2nd Clock - Enables second output clock for LPDDR3 packages/topologies with two clocks

Address Copy - Duplicates the address/command interfaces for LPDDR3 packages/topologies with two CA interfaces

2tCK Command Timing (2T) - Enable 2tCK command timing (2T timing) on the DDR3/DDR4 Command/Address/Control bus signals. This feature can be used as a workaround to address signal quality problems on the CAC bus caused by the sub-optimal board layouts or power quality issues.