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Zynq UltraScale+ MPSoC Processing System Product Guide (PG201)

Document_ID
PG201
Release_Date
2022-05-11
Version
3.4 English

• PL to PS Cross Trigger Inputs – Trigger signals, four pairs from the PL. Each pair consists of a trigger signal and an acknowledge signal, and follows the Arm® standard CTI handshake protocol.

• PL to PS Cross Trigger Outputs and sub options – Trigger signals, four pairs to the PL. Each pair consists of a trigger signal and an acknowledge signal, and follows the Arm® standard CTI handshake protocol.

• GP Input[0:31] GP Output[0:31] – General purpose I/Os, 32 bits to the PL and 32 bits from the PL. These are accessed through reads and writes to registers.