For more information, see the Zynq UltraScale All Programmable MPSoC Technical Reference Manual (UG1085) [Ref 1] .
• CSU Register – Setting bits in this register causes the CSU ROM to issue a system interrupt when the tamper event occurs.
• External MIO – Observation of MIOs that causes the CSU ROM to issue a system interrupt when the tamper event occurs.
• JTAG toggle detect – Bit to identify the change in the JTAG mode.
• PLU SEU error – Bit to indicate Single Even Upset error.
• Temp Alarm for LPD – Temperature alarm for Low Power/RPU domain.
• Temp Alarm for APU – Temperature alarm for APU/ Full power domain.
• Voltage Alarm for VCCPINT_FPD – Power rail removal alarm when VCCPINT_FPD is removed.
• Voltage Alarm for VCCPINT_LPD – Power rail removal alarm when VCCPINT_LPD is removed.
• Voltage Alarm for VCCPAUX – Power rail removal alarm when VCCPAUX is removed.
• Voltage Alarm for DDRPHY – Reference voltage observation signal for DDR PHY.
• Voltage Alarm for PSIO bank 0/1/2 – Reference voltage observation signal for PSIO bank 0/1/2.
• Voltage Alarm for PSIO bank 3 – Reference voltage observation signal for PSIO bank 3.
• Voltage Alarm for GT – Reference voltage observation signal for Gigabit transceivers.