Master Interface - 3.4 English - PG201

Zynq UltraScale+ MPSoC Processing System Product Guide (PG201)

Document ID
PG201
Release Date
2022-05-11
Version
3.4 English

° AXI HPM0 FPD – High performance master 0 in full power domain

° AXI HPM1 FPD – High performance master 1 in full power domain

° AXI HPM0 LPD – High performance master 0 in low power domain.

Each interface supports 32, 64, and 128 data widths.