Low Power Domain Clocks - 3.4 English - PG201

Zynq UltraScale+ MPSoC Processing System Product Guide (PG201)

Document ID
PG201
Release Date
2022-05-11
Version
3.4 English

Processor/Memory Clocks – Clock configuration for the CPU_R5 Processor

Peripherals/IO Clocks – Clock configuration for low-speed peripheral devices.

PL Clocks – PS generated clock to PL: PL0, PL1, PL2, and PL3

System Debug Clocks – Clock configuration for debug modules DBG_LPD