Known Limitations - 3.4 English

Zynq UltraScale+ MPSoC Processing System Product Guide (PG201)

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3.4 English

By default, Isolation settings are partially applied by First Stage Boot Loader (FSBL). FSBL will not configure Isolation settings for Peripherals. Isolation settings for DDR and OCM XMPU only will be configured by FSBL through psu_init. To apply the Isolation settings completely, compile FSBL with FSBL_PROT_BYPASS_EXCLUDE_VAL symbol.

CCI_GPV and FPD_GPV regions are not protected by XPPU/XMPU. So any secure master can access these regions even user configure these regions under isolation page.