High Speed - 3.4 English - PG201

Zynq UltraScale+ MPSoC Processing System Product Guide (PG201)

Document ID
PG201
Release Date
2022-05-11
Version
3.4 English

Pins from high-speed peripherals, like, PCIe, SATA, Gigabit Ethernet Module (GEM) (in SGMII mode), Display Port and USB 3.0 can be routed to SERDES by selecting the appropriate GT lanes in the I/O column.