General Design Guidelines - 3.4 English

Zynq UltraScale+ MPSoC Processing System Product Guide (PG201)

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3.4 English

There are three interfaces through which the Zynq® UltraScale+™ Processing System core can access the PL side peripherals and vice versa. For more details, see the individual sections of AXI_HP and AXI_ACP interfaces in the “Interconnect” chapter of the Zynq UltraScale All Programmable MPSoC Technical Reference Manual (UG1085) [Ref 1] .