Full Power Domain Clocks - 3.4 English - PG201

Zynq UltraScale+ MPSoC Processing System Product Guide (PG201)

Document ID
PG201
Release Date
2022-05-11
Version
3.4 English

Processor/Memory Clocks – Clock configuration for A53 CPU (ACPU), GPU, and DDR

Peripherals/IO Clocks – Clock configuration for high-speed peripheral devices.

System Debug Clocks – Clock configuration for debug modules: DBG_FPD,DBG_TRACE, and DBG_TSTMP